Intel Itanium Arcgitecture
Advanced Computer Architecture Assignment-II
P.VINOTHINI CSE-B
Intel Itanium Architecture
Intel Itanium Architecture or IA-64: Intel and Hewlett-Packard developed the Itanium processor jointly. The Itanium is also called IA-64 (Intel Architecture 64 bit processor) uses 64-bit registers and performs 64-bit arithmetic and logic operations (figure 1). The Itanium architecture also provides full compatibility with Intel's 32-bit architecture also known as IA-32.
[pic]
Figure1: 64-bit registers in an Itanium chipset.
The working operations of various registers that are used in an Itanium chipset are as follows:
1. Integer Register:128 64-bit+1bit NaT general registers and are shown by GR0 to GR127. GR0 is hardwired to zero, thus the content of it is set to zero. Figure 2 shows general register with an extra bit called Not a Thing (NaT)
Figure 2:
[pic]
Figure 2: General register with an extra bit called Not a Thing (NaT).
2. Floating Point Register: 128 82-bit floating point registers represented by FR0 through FR127, where FR0 and FR1 are set to zero and 1 respectively.
3. Qualify Predicate Register: 64 1-bit predicate register represented by P0, P1, P2, P3… P63, where P0 is set to zero. When the value of Pi is true (=1), the instruction using Pi is executed and when value of Pi for an instruction is false (0), the instruction act as NOP.
4. Branch Register: 8 64-bit Branch Registers are represented by br0 through br7.
5. Loop Count (LC) Register: The Loop Count (LC) register is a 64-bit counter that is used for counting loops. 6. Current Frame Maker (CFM) Register: CMF register is a 38-bit register and is used to represent register stack.
7. Instruction Pointer (IP): The 64-bit instruction pointer holds the address of the bundle of the currently executing instruction. Each bundle consists of three instructions and a 5-bit template.
P.VINOTHINI CSE-B
Intel Itanium Architecture
Intel Itanium Architecture or IA-64: Intel and Hewlett-Packard developed the Itanium processor jointly. The Itanium is also called IA-64 (Intel Architecture 64 bit processor) uses 64-bit registers and performs 64-bit arithmetic and logic operations (figure 1). The Itanium architecture also provides full compatibility with Intel's 32-bit architecture also known as IA-32.
[pic]
Figure1: 64-bit registers in an Itanium chipset.
The working operations of various registers that are used in an Itanium chipset are as follows:
1. Integer Register:128 64-bit+1bit NaT general registers and are shown by GR0 to GR127. GR0 is hardwired to zero, thus the content of it is set to zero. Figure 2 shows general register with an extra bit called Not a Thing (NaT)
Figure 2:
[pic]
Figure 2: General register with an extra bit called Not a Thing (NaT).
2. Floating Point Register: 128 82-bit floating point registers represented by FR0 through FR127, where FR0 and FR1 are set to zero and 1 respectively.
3. Qualify Predicate Register: 64 1-bit predicate register represented by P0, P1, P2, P3… P63, where P0 is set to zero. When the value of Pi is true (=1), the instruction using Pi is executed and when value of Pi for an instruction is false (0), the instruction act as NOP.
4. Branch Register: 8 64-bit Branch Registers are represented by br0 through br7.
5. Loop Count (LC) Register: The Loop Count (LC) register is a 64-bit counter that is used for counting loops. 6. Current Frame Maker (CFM) Register: CMF register is a 38-bit register and is used to represent register stack.
7. Instruction Pointer (IP): The 64-bit instruction pointer holds the address of the bundle of the currently executing instruction. Each bundle consists of three instructions and a 5-bit template.