Assignment 3

Chapter 4
16. All
17. Accessing ports without disturbing the other ports
27. 5
Chapter 5
5. Push
7. Moves 1F directly to A
9. In this mode the registers are used as a pointer to the data. R0 and R1 are the only registers used in this addressing mode
17. All ports P0 to P3 are bit addressable
18. 16 bytes of the internal ram are bit addressable. The locations are 20H to 2FH
24. P0-80H-87H
25. P1-90H-97H
26. P2-A0H-A7H
27. P3-B0H-B7H
28. PCON-98H-98FH
29. TCON-88H-8FH
35. CLR.PSW.&
37. MOV A, D0H (D0H is the address of PSW
ANL A, FBH (Mask the unused bits and test the ones needed)
MOV P1, A (Display for the user on the board)
Chapter 4
20. CPL P1.2 CPL P1.5 SJMP H1
24. SET B, P2.0 ; MAKE P2.0 AN INPUT AGAIN:JB P2.0,OVER ;JUMP IF P1.4=1 SJMP AGAIN ;KEEP MONITORING OVER: MOV P1, #66H ;SW=0,ISSUE 66H TO P1 SJMP AGAIN ;KEEP MONITORING END
Chapter 5
8. PUSH 00 PUSH 01 PUSH 03 POP 05 POP 06 POP 07
10. MOV R7, #1FH MOV R1, 50H MOV R4, #0FFH
AGAIN:
MOV @R1,R4 INC R1 DJNZ R7 SJMP AGAIN 13. MOV DPTR, DB 06,09,02,05,07 MOV 30H, #00H MOV R1, #00H LOOP: MOVC A, @A+DPTR ADD A, 30H MOV 30H, A INC R1 MOV A,R1 CJNE R1,#05H, LOOP
20. SETB P1.5 LCALL DELAY LCALL DELAY LCALL DELAY CLR P1.5 LCALL DELAY LCALL DELAY LCALL DELAY SJMP HERE
23. SETB P2.1 MOV A, #55H JNB P2.1,AGAIN MOV PO,A MOV P2.2 SETB 2.2 CLR 2.2

67. ORG 0 MOV A,#55H MOV R2, #10 MOV R0, #C0
BACK: MOV @R0,A INC R0 DJNZ R2, BACK SJMP $ END