Computer and Adders
FAST VLSI BINARY ADDITION
Dept. of Electrical and Computer Engineering University of Minnesota, Minneapolis, MN 55455, USA E-mail: parhi@ee.umn.edu
Keshab K. Parhi
Abstract - This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wtfa to Wtmux where tfa and tmux , respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carrygeneration component is the critical component in redundant-to-binary conversion and binary addition. It is shown that, if the word-length, W , is a power of two, then all carry signals can be generated in log2 Wtmux time using W (log2 W ? 1) + 1 multiplexers using a tree-type converter. It is shown that fastest binary addition can be performed using (Wlog2 W + 1) multiplexers in time (log2 W + 1)tmux . If the speci ed converter latency is greater than log2 Wtmux, then a family of converters using fewest multiplexers can be designed based on carry-select approach. It is shown that the power consumption in carry-select adders is minimized by increasing the number of segments in the adder.
Binary addition is one of the primitive operations in computer arithmetic. The well known ripple carry adder can add two W -bit binary numbers using W binary full adders with latency Wtfa where tfa represents the binary full adder delay 1]. Fast addition can be carried out using various fast adders such as carry-select adder 2] or binary look-ahead adder 3]. These fast adders can also be implemented e ciently using multiplexers only. Another approach to designing much faster
Dept. of Electrical and Computer Engineering University of Minnesota, Minneapolis, MN 55455, USA E-mail: parhi@ee.umn.edu
Keshab K. Parhi
Abstract - This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wtfa to Wtmux where tfa and tmux , respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carrygeneration component is the critical component in redundant-to-binary conversion and binary addition. It is shown that, if the word-length, W , is a power of two, then all carry signals can be generated in log2 Wtmux time using W (log2 W ? 1) + 1 multiplexers using a tree-type converter. It is shown that fastest binary addition can be performed using (Wlog2 W + 1) multiplexers in time (log2 W + 1)tmux . If the speci ed converter latency is greater than log2 Wtmux, then a family of converters using fewest multiplexers can be designed based on carry-select approach. It is shown that the power consumption in carry-select adders is minimized by increasing the number of segments in the adder.
Binary addition is one of the primitive operations in computer arithmetic. The well known ripple carry adder can add two W -bit binary numbers using W binary full adders with latency Wtfa where tfa represents the binary full adder delay 1]. Fast addition can be carried out using various fast adders such as carry-select adder 2] or binary look-ahead adder 3]. These fast adders can also be implemented e ciently using multiplexers only. Another approach to designing much faster
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