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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 20, NO. 2, FEBRUARY 2010

An Efficient Architecture for 3-D Discrete Wavelet Transform
Anirban Das, Anindya Hazra, and Swapna Banerjee, Senior Member, IEEE

Abstract—This paper presents an architecture of the liftingbased running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3-DDWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput compared to those of earlier reported works. The proposed architecture has been successfully implemented on Xilinx Virtex-IV series field-programmable gate array, offering a speed of 321 MHz, making it suitable for realtime compression even with large frame dimensions. Moreover, the architecture is fully scalable beyond the present coherent Daubechies filterbank (9, 7). Index Terms—Discrete wavelet transform, image compression, lifting, video, VLSI architecture.

I. Introduction

S

TILL IMAGE compression technique based on 2-D discrete wavelet transform (DWT) has already gained superiority over traditional JPEG based on discrete cosine transform and is standardized in forms like JPEG2000 [1]. Quite similarly, the application of its 3-D superset, i.e., 3-D-DWT on video, outperforms the current predictive coding standards, like H.261-3, MPEG1-2,4 by rendering the quality features like better peak signal-to-noise ratio (PSNR), absence of blocky artifacts in low bit rates. Furthermore, it has the added provisions of highly scalable compression, which is mostly coveted in modern communications over heterogeneous channels like the Internet [2]. Successful application of 3-D-DWT has been reported in the literature in

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Conclusion The applications of 3-D wavelet based coding are opening new vistas in video and other multidimensional signal compression and processing. The prominent needs in these diversified application areas are efficient 3-D-DWT engines with good computing power which draws the attention of the dedicated VLSI architectures as the best possible solution. Though the researches of 2-D-DWT architectures are progressing quite fast, fewer approaches are reported in the literatures designing their 3-D counterpart. 296 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 20, NO. 2, FEBRUARY 2010 [11] W. Badawy, M. Weeks, G. Zhang, M. Talley, and M. A. Bayoumi, “MRI data compression using a 3-D discrete wavelet transform,” IEEE Eng. Med. Biol. Mag., vol. 21, no. 4, pp. 95–103, Jul.–Aug. 2002. [12] J. Xu, Z. Xiong, S. Li, and Y.-Q. Zhang, “Memory-constrained 3-D wavelet transform for video coding without boundary effects,” IEEE Trans. Circuits Syst. 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Zhang, “Motion compensated lifting wavelet and its application in video coding,” in Proc. IEEE Int. Conf. Multimedia Expo, Tokyo, Japan, 2001, pp. 365–368. [28] Architecture and Features of a Fully Scalable Motion-Compensated 3-D Subband Codec, document M7977.doc, ISO/IEC/JTC1/SC29/ WG11, Mar. 2002. [29] Improved MC-EZBC with Quarter-Pixel Motion Vectors, document 813 MPEG2002/M8366, ISO/IEC JTC1/SC29/WG11, May 2002. Anirban Das received the B.E. degree in electronics and telecommunication engineering from Bengal Engineering and Science University, Shibpur, India, and the M.S. degree in electronics and electrical communication engineering from the Indian Institute of Technology Kharagpur, Kharagpur, India. His M.S. thesis title was “Lifting based architecture for realizing two and 3-D discrete wavelet transform.” His research work was related to the design of highly efficient reduced memory 2-D and 3-D discrete wavelet transform architectures to be used in lossless and lossy image and video compression systems. Since 2006, he has been with the Bangalore Design Center, Nvidia Corporation, Bangalore, India, where he holds the position of an ApplicationSpecific Integrated Circuit Design Engineer, working on Nvidia’s latest motherboard graphics processors. His research interests include multimedia and signal processing architectures, platform architectures, system-on-chip design, and controller design of industry standard bidirectional universal switches. Anindya Hazra received the B.E. degree in electronics and telecommunication engineering from Bengal Engineering and Science University, Shibpur, India, in 2002, and the M.S. degree in electronics and electrical communication engineering from the Indian Institute of Technology Kharagpur, Kharagpur, India, in 2005. From 2005 to 2006, he was with the Computer Maintenance Corporation Ltd., Hyderabad, India. He is currently a Complex Digital Designer at the STMicroelectronics Private Ltd., Greater Noida, Uttar Pradesh, India. His research interests include image and video processing architecture, and complex system-on-chip design. Swapna Banerjee (SM’99) received the B.E. and M.E. degrees from the Department of Electronics and Telecommunication Engineering, Jadavpur University, Jadavpur, India, in 1971 and 1974, respectively. She received the Ph.D. degree from the Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India, in 1981. She is currently a Professor at the Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur. She has published in several reputed journals and conferences. She has served as a mentor for a number of doctoral students over the last two decades. She is supervising a number of projects funded by national and international agencies, mainly related to VLSI-DSP-based noninvasive biomedical instrumentations. Her research interests include analog and digital VLSI design, and digital signal/image processing for biomedical instrumentations. Dr. Banerjee received the Postdoctoral Fellowship from Tokyo University, Tokyo, Japan. She received the prestigious Matsumae International Foundation Award in 1985.