ECET230 Lab1 Procedures
I. OBJECTIVES
1. To understand how to describe basic circuits using VHDL
2. To compile and simulate a VHDL text file
3. To learn how to assign pins for a desired circuit to the eSOC II board
4. To download a program to the eSOC II board and verify that the programmed circuit operates as designed
II. PARTS LIST
Equipment: IBM PC or Compatible with Windows 2000 or Higher Quartus II Design Software – Version 9.1
Parts:
eSOC II Board
III. INTRODUCTION
The circuit design for this Lab is entered using Computer Aided Engineering (CAE) design tools for Altera’s programmable logic family. These tools allow the complete design, compilation, simulation, verification, and programming of a programmable logic IC to be done in one simple, user-friendly design environment.
The first step is to enter the design for processing, called DESIGN ENTRY. This is usually done in two different ways. The first way is called schematic capture and requires a schematic for the logic design. The schematic uses graphical symbols to represent logic gates and functions, which are connected using graphical wires similar to Electronic Work Bench.
The second method of DESIGN ENTRY is to use a specialized programming language called VHDL (Very high-speed integrated circuit Hardware Description Language). This method is used in this and future Labs.
The next step is to COMPILE the design. This creates a design netlist that describes the interconnections between gates and IO pins and routes these connections within the programmable logic IC. The logic design is minimized (reduced) and any compilation errors are shown. The COMPILE also generates timing files that are used in the simulation and programming files that are used to program the chip.
The next step is to SIMULATE the logic design. This is a verification step used to analyze the functionality of a design. Simulation allows us the chance of verifying a design without actually building the circuit. The
1. To understand how to describe basic circuits using VHDL
2. To compile and simulate a VHDL text file
3. To learn how to assign pins for a desired circuit to the eSOC II board
4. To download a program to the eSOC II board and verify that the programmed circuit operates as designed
II. PARTS LIST
Equipment: IBM PC or Compatible with Windows 2000 or Higher Quartus II Design Software – Version 9.1
Parts:
eSOC II Board
III. INTRODUCTION
The circuit design for this Lab is entered using Computer Aided Engineering (CAE) design tools for Altera’s programmable logic family. These tools allow the complete design, compilation, simulation, verification, and programming of a programmable logic IC to be done in one simple, user-friendly design environment.
The first step is to enter the design for processing, called DESIGN ENTRY. This is usually done in two different ways. The first way is called schematic capture and requires a schematic for the logic design. The schematic uses graphical symbols to represent logic gates and functions, which are connected using graphical wires similar to Electronic Work Bench.
The second method of DESIGN ENTRY is to use a specialized programming language called VHDL (Very high-speed integrated circuit Hardware Description Language). This method is used in this and future Labs.
The next step is to COMPILE the design. This creates a design netlist that describes the interconnections between gates and IO pins and routes these connections within the programmable logic IC. The logic design is minimized (reduced) and any compilation errors are shown. The COMPILE also generates timing files that are used in the simulation and programming files that are used to program the chip.
The next step is to SIMULATE the logic design. This is a verification step used to analyze the functionality of a design. Simulation allows us the chance of verifying a design without actually building the circuit. The