hello to everyone

Introduction to
Layout design

Note: some figures are taken from Ref. B. Razavi, Design of Analog CMOS integrated circuits, Mc Graw-Hill, 2001, and MOSIS web site: http://www.mosis.org/ 1
E. Martinez-Guerrero /Taller de Diseño Físico / MDE_DESI_ITESO/Otoño 2006

Introduction to layout design
Layout consist in:
Draw geometrical objects of different layers,
Make arrays of geometrical objects,
Patterns
Make blocks of arrays for the core, interface, for the and padframe. fabrication the
Interconnect blocks and interfaces to the
“masks”
padframe,
All the layout must satisfy “design rules”

Why design rules?
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E. Martinez-Guerrero /Taller de Diseño Físico / MDE_DESI_ITESO/Otoño 2006

Layers for designs masks used by L-Edit
Default SCNA CMOS Layers
Physical layer

Name

Color

N-well

N-WELL

TAN dashed

SiN3

ACTIVE

GREEN filled

Polysilicon 1

POLY1

RED filled

Polysilicon 2

POLY2

BLACK filled

Contact to poly

POLY CONTACT

BLACK filled

P+ Ion implant

PSELECT

RED dashed

N+ Ion implant

NSELECT

TAN dashed

Contact to N+/P+ ACTIVE CONTACT

BLACK filled

Metal 1

METAL 1

BLUE filled

Metal 2

METAL 2

GREY filled

Via oxide cuts

VIA

WHITE filled

Pad contacts

OVERGLASS

Purple crosshatch

E. Martinez-Guerrero /Taller de Diseño Físico / MDE_DESI_ITESO/Otoño 2006

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Considerations in layout of CMOS

D

G

S

Basic layout of a MOSFET
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E. Martinez-Guerrero /Taller de Diseño Físico / MDE_DESI_ITESO/Otoño 2006

Considerations in layout of CMOS
Changes in W due to tolerances in the fabrication process oxide encroachment

D

FOX

FOX

G
Drawn Width

p-substrate

S

bird’s beak
FOX

FOX gate oxide

FOX
FOX

FOX

W
DW/2
p-substrate

W

ideal real E. Martinez-Guerrero /Taller de Diseño Físico / MDE_DESI_ITESO/Otoño 2006

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Considerations in layout of CMOS
Changes in L due to tolerances in the fabrication