DeVry University
College of Engineering and Information Sciences
Course Number: ECET-230
Professor:
Laboratory Number:
Laboratory Title: Introduction to Quartus II, VHDL, and the FPGA Board
Submittal Date:
Objectives:
Results:
Conclusions:
Team:
Name
Program
Signature
Name
Program
Signature
Name
Program
Signature
Observations/Measurements:
Describe any problems you had with using Quartus II and/or the eSOC III board.
Questions:
1. Using the results of the compilation for the Design Project, what percent of the FPGA is used to implement the design.
<1%
2. In the compilation process, what is the difference between an error and a warning?
error is a problem that will cause the program not to run. The Warning is advisor to a issue that may result as a bad input or output.
3. Use the zoom tool to measure the propagation delays, tPHL and tPLH, for the FPGA implementing the Design Project (the times between an input change of state and the subsequent output change of state in response). The zoom tool is used by expanding the time scale, right clicking on one signal and selecting “Insert Time Bar.”
tPHL = 0.014763
tPLH = 0.015349
4. What is “JTAG” and why is it used? Be sure to cite your sources.
IEEE – Test access point
Grade:
Deliverable
Points Available
Points Achieved
Laboratory Cover Sheet
8
Working Circuit(s)/Program(s)
8
Observations/Measurements
6
Questions
8
Total Points
30
Comments: