Manuals
Banlawe, Ivane Ann P.
David, Joana Haizan G.
Landicho, Lloyd Charles L.
Mapuá Institute of Technology
2012
LE Design Verification
Table of Contents
Table of Contents
Cover Page
i
Table of Contents
ii
I.
Introduction
1
II.
Running DRC (Design Rule Check)
2
III. Running LVS (Layout Versus Schematic)
5
IV. Running LPE (Layout Parasitic Extraction)
8
V. Reference
Compiled by: Banlawe, Ivane Ann P.
David, Joana Haizan G.
Landicho, Lloyd Charles L.
13
ii
LE Design Verification
Introduction
I. Introduction
DESIGN RULE CHECK (DRC)
Design Rule Checking or Check(s) (DRC) is the area of Electronic Design Automation that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules.
Some examples of DRC’s in IC design include:
■
Active to active spacing
■
Well to well spacing
■
Minimum channel length of the transistor
■
Minimum metal width
■
Metal to metal spacing
LAYOUT VERSUS SCHEMATIC (LVS)
The LVS (Layout versus Schematic) check performs LVS comparison to verify that the design layout accurately represents the electronic equivalent of the design schematic. Hercules LVS verifies whether the physical design matches the schematic by: extracting the devices, verifying the connectivity between the devices and comparing the extracted information with the schematic netlist.
Notice that in order to pass LVS, schematic names and layout names must match one to one.
Make sure the names for labels and pins are using uppercase letters instead of lowercase letters. Also transistor dimensions for gate width and length in layout and schematic must match.
LAYOUT PARASITIC EXTRACTION (LPE)
After passing DRC and LVS you can now move on to LPE (Layout Parasitic Extraction). In this phase, resistive and capacitive components will be extracted from the layout.
Compiled by: Banlawe, Ivane Ann P.
David, Joana Haizan G.
Landicho, Lloyd Charles L.
Mapuá Institute of Technology
2012
LE Design Verification
Table of Contents
Table of Contents
Cover Page
i
Table of Contents
ii
I.
Introduction
1
II.
Running DRC (Design Rule Check)
2
III. Running LVS (Layout Versus Schematic)
5
IV. Running LPE (Layout Parasitic Extraction)
8
V. Reference
Compiled by: Banlawe, Ivane Ann P.
David, Joana Haizan G.
Landicho, Lloyd Charles L.
13
ii
LE Design Verification
Introduction
I. Introduction
DESIGN RULE CHECK (DRC)
Design Rule Checking or Check(s) (DRC) is the area of Electronic Design Automation that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules.
Some examples of DRC’s in IC design include:
■
Active to active spacing
■
Well to well spacing
■
Minimum channel length of the transistor
■
Minimum metal width
■
Metal to metal spacing
LAYOUT VERSUS SCHEMATIC (LVS)
The LVS (Layout versus Schematic) check performs LVS comparison to verify that the design layout accurately represents the electronic equivalent of the design schematic. Hercules LVS verifies whether the physical design matches the schematic by: extracting the devices, verifying the connectivity between the devices and comparing the extracted information with the schematic netlist.
Notice that in order to pass LVS, schematic names and layout names must match one to one.
Make sure the names for labels and pins are using uppercase letters instead of lowercase letters. Also transistor dimensions for gate width and length in layout and schematic must match.
LAYOUT PARASITIC EXTRACTION (LPE)
After passing DRC and LVS you can now move on to LPE (Layout Parasitic Extraction). In this phase, resistive and capacitive components will be extracted from the layout.
Compiled by: Banlawe, Ivane Ann P.
References: Reference Chan M., Mahmoodi H., Norouzi M., Full Custom IC Design Flow Tutorial Using Synopsys Custom Tools, Nano-Electronics & Computing Research Lab, San Francisco State University, 2010 Compiled by: Banlawe, Ivane Ann P. David, Joana Haizan G. Landicho, Lloyd Charles L. 13