Microprocessor without Interlocked Pipeline Stages Architecture

MIPS Architecture
 MIPS stands for 'Microprocessor without Interlocked

Pipeline Stages’  RISC Instruction Set Architecture  32 bit general purpose registers  PC (program counter) holds address of next instruction  all MIPS Instructions are same length  Few Instruction formats and simple addressing modes

Implementing MIPS
• • Implementation of the MIPS instruction set Simplified to contain only
– arithmetic-logic instructions: add, sub, and, or, slt – memory-reference instructions: lw, sw – control-flow instructions: beq, j
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op
6 bits

rs
5 bits

rt
5 bits

rd

shamt funct
16 bits

R-Format

op
6 bits

rs

rt
26 bits

offset

I-Format J-Format

op

address

MIPS Instruction Format
• An instruction like “add” consists of 6 fields op 6

rs
5

rt
5

rd
5

shamt funct
5 6

 op: opcode

    

rs: first register source operand rt: second register source operand rd: register destination shamt: shift amount (see later) funct: function code (to select a variant of the operation, based on the opcode)

Overview: Processor Implementation Styles
• Single Cycle
– perform each instruction in 1 clock cycle – clock cycle must be long enough for slowest instruction; therefore, – disadvantage: only as fast as slowest instruction

• Multi-Cycle
– break fetch/execute cycle into multiple steps – perform 1 step in each clock cycle – advantage: each instruction uses only as many cycles as it needs

• Pipelined
– execute each instruction in multiple steps – perform 1 step / instruction in each clock cycle – process multiple instructions in parallel – assembly line

Implementing MIPS: the Fetch/Execute Cycle
• High-level abstract view of fetch/execute implementation
– – – – – use the program counter (PC) to read instruction address fetch the instruction from memory and increment PC use fields of the instruction to select registers to read execute depending