Modified Booth Encoding Radix-4 8-Bit Multiplier
Modified Booth Encoding Radix-4 8-bit Multiplier
Final Project Report
Da Huang, Afsaneh Nassery
Table of Contents
Table of Contents ...................................................................................................................... 2 Abstract: .................................................................................................................................... 3 System Diagram:............................................................................................................... 3 Performance Estimation: ................................................................................................... 5 Transistor number and Area estimation .................................................................... 5 Time Delay:............................................................................................................... 6 Power Consumption: ................................................................................................. 6 Project Floor plane: ........................................................................................................... 7 Sub circuit Design ..................................................................................................................... 8 Encoder Circuit ............................................................... Error! Bookmark not defined. Decoder Circuit ............................................................... Error! Bookmark not defined. 12 Bit Adder circuit......................................................................................................... 12 Full System Design ................................................................................................................. 13 Test simulations………………………………………………………………………… 16 Summary ................................................................................. Error! Bookmark not defined. Reference
Final Project Report
Da Huang, Afsaneh Nassery
Table of Contents
Table of Contents ...................................................................................................................... 2 Abstract: .................................................................................................................................... 3 System Diagram:............................................................................................................... 3 Performance Estimation: ................................................................................................... 5 Transistor number and Area estimation .................................................................... 5 Time Delay:............................................................................................................... 6 Power Consumption: ................................................................................................. 6 Project Floor plane: ........................................................................................................... 7 Sub circuit Design ..................................................................................................................... 8 Encoder Circuit ............................................................... Error! Bookmark not defined. Decoder Circuit ............................................................... Error! Bookmark not defined. 12 Bit Adder circuit......................................................................................................... 12 Full System Design ................................................................................................................. 13 Test simulations………………………………………………………………………… 16 Summary ................................................................................. Error! Bookmark not defined. Reference