Modified Iterative Logarithmic Multiplier
Abstract
A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. many researchers have tried and are trying to design multipliers which offer either of the following- high speed, low power consumption, less area, more accuracy or even combination of them in multiplier.
However, in multiplier design for reducing time and power consumption there are many practical solutions, like truncated and logarithmic multipliers. These methods consume less time and power but introduce errors.
Nevertheless, they can be used in situations where a shorter time delay is more important than accuracy. But, in many applications where accuracy is prime criteria they have drawbacks
This thesis presents a simple and efficient multiplier with the possibility to achieve an maximum accuracy with less area and low power Consumption through an iterative procedure and recursive logic. The multiplier is based on the same form of number representation as Mitchell’s algorithm, but for error correction it uses different algorithm proposed by Z. Babic, A. Avramovic , P. Bulic. And to make it more efficient error correction is done using recursive logic. In such a way, the error correction can be done almost in parallel (actually this is achieved through pipelining) with the basic multiplication and The hardware solution involves adders and shifters, so without much gates are involve it is less area and power consuming .
In order to evaluate the performance of the proposed multiplier, we implemented different multipliers on the Xilinx xc3s1500-5fg676 FPGA. We implemented four 16-bit reported multipliers: a pipelined multiplier with no correction terms and three pipelined multipliers with one, two and three correction terms and one 16-bit proposed multiplier.
Introduction
Multiplication has always been a hardware, time and power consuming arithmetic operation,
A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. many researchers have tried and are trying to design multipliers which offer either of the following- high speed, low power consumption, less area, more accuracy or even combination of them in multiplier.
However, in multiplier design for reducing time and power consumption there are many practical solutions, like truncated and logarithmic multipliers. These methods consume less time and power but introduce errors.
Nevertheless, they can be used in situations where a shorter time delay is more important than accuracy. But, in many applications where accuracy is prime criteria they have drawbacks
This thesis presents a simple and efficient multiplier with the possibility to achieve an maximum accuracy with less area and low power Consumption through an iterative procedure and recursive logic. The multiplier is based on the same form of number representation as Mitchell’s algorithm, but for error correction it uses different algorithm proposed by Z. Babic, A. Avramovic , P. Bulic. And to make it more efficient error correction is done using recursive logic. In such a way, the error correction can be done almost in parallel (actually this is achieved through pipelining) with the basic multiplication and The hardware solution involves adders and shifters, so without much gates are involve it is less area and power consuming .
In order to evaluate the performance of the proposed multiplier, we implemented different multipliers on the Xilinx xc3s1500-5fg676 FPGA. We implemented four 16-bit reported multipliers: a pipelined multiplier with no correction terms and three pipelined multipliers with one, two and three correction terms and one 16-bit proposed multiplier.
Introduction
Multiplication has always been a hardware, time and power consuming arithmetic operation,