Output and Decoder
CSCE 211: Digital Logic Design Fall 2013
Homework 4 (Section 001 – Regular Section) 10/22/13
This homework consists of 7 questions. Please find the corresponding questions from Section 5.10 in your textbook.
Follow this link to find Decoder and MUX instructions: http://www.cse.sc.edu/~huangct/CSCE211F13/Function-MUX-Decoder.htm Follow this link to find 3-to-8 Decoder, 74LS138: http://www.cse.sc.edu/~huangct/CSCE211F13/74x138.pdf Follow this link to find 8-to-1 MUX, 74LS151: http://www.cse.sc.edu/~huangct/CSCE211F13/74x151.pdf 1. (0.2 points) Problem 1.a.i and 1.b from Section 5.10. Assume that there is a small delay ∆ at each gate (from the input to the output).
2. (0.3 points) Problem 7 from Section 5.10. Simply find the minterm numbers for X and Y from the diagram.
3. (0.5 points) Use an 8-to-1 MUX (74LS151 above) to implement f(W, X, Y, Z) = ∑m(0, 1, 3, 6, 9, 12, 15). Pair rows (0-1, 2-3, ...) so that MUX inputs are 0, 1, Z, or Z'. Show chip enabled, connect variables to address lines, and label function output.
4. (0.5 points) Use a 3-to-8 DECODER (74LS138 above) and an external gate AND or NAND with the fewest inputs to implement f(x, y, z) = ∑m(1, 2, 4, 5, 7). (Hint: AND the Maxterms, NAND the minterms.) Show chip enabled, connect variables to address lines, and label the function output.
5. (0.5 points) Problem 9 from Section 5.10. Build a 3-to-8 decoder by "stacking" two 2-to-4 decoders with an active low enables. See page 312. Use the most significant function variable "a" and an external inverter to enable the correct decoder. Variables "b" and "c" are connected to decoder lines "A (MS)" and "B". Label the decoder outputs m0 to m3 (top) and m4 to m7 (bottom).
6. (0.5 points) Problem 12 from Section 5.10 using a 4-to-1 MUX and row pairing. Assume z' is available.
7. (0.5 points) For the following set of functions, design a system (i) using a ROM; and (ii) using a PAL. F(A, B, C, D) = A'CD + BC' G(A, B,
Homework 4 (Section 001 – Regular Section) 10/22/13
This homework consists of 7 questions. Please find the corresponding questions from Section 5.10 in your textbook.
Follow this link to find Decoder and MUX instructions: http://www.cse.sc.edu/~huangct/CSCE211F13/Function-MUX-Decoder.htm Follow this link to find 3-to-8 Decoder, 74LS138: http://www.cse.sc.edu/~huangct/CSCE211F13/74x138.pdf Follow this link to find 8-to-1 MUX, 74LS151: http://www.cse.sc.edu/~huangct/CSCE211F13/74x151.pdf 1. (0.2 points) Problem 1.a.i and 1.b from Section 5.10. Assume that there is a small delay ∆ at each gate (from the input to the output).
2. (0.3 points) Problem 7 from Section 5.10. Simply find the minterm numbers for X and Y from the diagram.
3. (0.5 points) Use an 8-to-1 MUX (74LS151 above) to implement f(W, X, Y, Z) = ∑m(0, 1, 3, 6, 9, 12, 15). Pair rows (0-1, 2-3, ...) so that MUX inputs are 0, 1, Z, or Z'. Show chip enabled, connect variables to address lines, and label function output.
4. (0.5 points) Use a 3-to-8 DECODER (74LS138 above) and an external gate AND or NAND with the fewest inputs to implement f(x, y, z) = ∑m(1, 2, 4, 5, 7). (Hint: AND the Maxterms, NAND the minterms.) Show chip enabled, connect variables to address lines, and label the function output.
5. (0.5 points) Problem 9 from Section 5.10. Build a 3-to-8 decoder by "stacking" two 2-to-4 decoders with an active low enables. See page 312. Use the most significant function variable "a" and an external inverter to enable the correct decoder. Variables "b" and "c" are connected to decoder lines "A (MS)" and "B". Label the decoder outputs m0 to m3 (top) and m4 to m7 (bottom).
6. (0.5 points) Problem 12 from Section 5.10 using a 4-to-1 MUX and row pairing. Assume z' is available.
7. (0.5 points) For the following set of functions, design a system (i) using a ROM; and (ii) using a PAL. F(A, B, C, D) = A'CD + BC' G(A, B,