Overlay Architectures for Fpga-Based Software Packet Processing
OVERLAY A RCHITECTURES FOR FPGA-BASED S OFTWARE PACKET P ROCESSING
by
Martin Labrecque
A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto
Copyright c 2011 by Martin Labrecque
Abstract
Overlay Architectures for FPGA-Based Software Packet Processing Martin Labrecque Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto 2011 Packet processing is the enabling technology of networked information systems such as the Internet and is usually performed with fixed-function custom-made ASIC chips. As communication protocols evolve rapidly, there is increasing interest in adapting features of the processing over time and, since software is the preferred way of expressing complex computation, we are interested in finding a platform to execute packet processing software with the best possible throughput. Because FPGAs are widely used in network equipment and they can implement processors, we are motivated to investigate executing software directly on the FPGAs. Off-the-shelf soft processors on FPGA fabric are currently geared towards performing embedded sequential tasks and, in contrast, network processing is most often inherently parallel between packet flows, if not between each individual packet. Our goal is to allow multiple threads of execution in an FPGA to reach a higher aggregate throughput than commercially available shared-memory soft multi-processors via improvements to the underlying soft processor architecture. We study a number of processor pipeline organizations to identify which ones can scale to a larger number of execution threads and find that tuning multithreaded pipelines can provide compact cores with high throughput. We then perform a design space exploration of multicore soft systems, compare single-threaded and multithreaded designs to identify scalability limits and
by
Martin Labrecque
A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto
Copyright c 2011 by Martin Labrecque
Abstract
Overlay Architectures for FPGA-Based Software Packet Processing Martin Labrecque Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto 2011 Packet processing is the enabling technology of networked information systems such as the Internet and is usually performed with fixed-function custom-made ASIC chips. As communication protocols evolve rapidly, there is increasing interest in adapting features of the processing over time and, since software is the preferred way of expressing complex computation, we are interested in finding a platform to execute packet processing software with the best possible throughput. Because FPGAs are widely used in network equipment and they can implement processors, we are motivated to investigate executing software directly on the FPGAs. Off-the-shelf soft processors on FPGA fabric are currently geared towards performing embedded sequential tasks and, in contrast, network processing is most often inherently parallel between packet flows, if not between each individual packet. Our goal is to allow multiple threads of execution in an FPGA to reach a higher aggregate throughput than commercially available shared-memory soft multi-processors via improvements to the underlying soft processor architecture. We study a number of processor pipeline organizations to identify which ones can scale to a larger number of execution threads and find that tuning multithreaded pipelines can provide compact cores with high throughput. We then perform a design space exploration of multicore soft systems, compare single-threaded and multithreaded designs to identify scalability limits and
Bibliography: [9] A LTERA C ORPORATION. Quartus II. http://www.altera.com. [10] A LTERA C ORPORATION. Accelerating http://www.altera.com/literature/an/an440.pdf, 2005. Nios II Ethernet applications. [28] C OOPERATIVE A SSOCIATION FOR I NTERNET DATA A NALYSIS. A day in the life of the Internet. WIDE-TRANSIT link, Jan. 2007. H EINRICH , J. MIPS RISC Architecture. Prentice Hall, 1992.