Phase Locked Loop
Phase Locked Loop:
The phase-lock-loop (PLL) is commonly used in microprocessors to generate a clock at high frequency (Fout=2GHz for example) from an external clock at low frequency (Fref = 100MHz for example). The PLL is also used as a clock recovery circuit to generate a clock signal from a series of bits transmitted in serial without synchronization clock (Figure below). The PLL may also be found in frequency demodulation circuits, to transform a frequency varying waveform into a voltage.
The PLL uses a high frequency oscillator with varying speed, a counter, a phase detector and a filter (figure below). The PLL includes a feedback loop which aligns the output clock ClkOut to the input clock ClkIn through a phase locking stabilization process. When locked, the high input frequency fout is exactly N. ƒin. A variation of the input frequency ƒin is transformed by the phase detector into a pulse signal, which is converted into variation of the analog signal Vc. This signal changes the VCO frequency, which is divided by the counter and changes clkDiv according to ƒin.
[pic]
Circuit Diagram
[pic]
Circuit Description
This circuit will function accurately over a 10:1 frequency range from 1 kHz to 10 kHz with the use of the CD4046 frequency detector. When an FIN edge occurs ahead of a F feedback pulse, pin 13 of the CD4046 pulls up on C1 via R1 = 1 kW. This current cannot be controlled or manipulated over as wide a range as “I1” in basic wide range phase locked loop (PLL). As a consequence, the response of this PLL is neither as smooth nor fast-settling as the basic PLL, but it is still better behaved than most F-to-V converters. Show a picture schematic:
Q1 = 2N3565 OR 2N3904 HIGH BETA NPN
A1, A2, A3 = 1/4 LM324
ON CD4046, PINS 1, 2, 4, 6, 7, 10, 11, 12 ARE NO CONNECTION
USE STABLE, LOW-T.C. PARTS FOR COMPONENTS MARKED*
VS = 7 TO 15 VDC
As with the basic PLL, the detector feeds a current to be integrated in C1 (and R2
The phase-lock-loop (PLL) is commonly used in microprocessors to generate a clock at high frequency (Fout=2GHz for example) from an external clock at low frequency (Fref = 100MHz for example). The PLL is also used as a clock recovery circuit to generate a clock signal from a series of bits transmitted in serial without synchronization clock (Figure below). The PLL may also be found in frequency demodulation circuits, to transform a frequency varying waveform into a voltage.
The PLL uses a high frequency oscillator with varying speed, a counter, a phase detector and a filter (figure below). The PLL includes a feedback loop which aligns the output clock ClkOut to the input clock ClkIn through a phase locking stabilization process. When locked, the high input frequency fout is exactly N. ƒin. A variation of the input frequency ƒin is transformed by the phase detector into a pulse signal, which is converted into variation of the analog signal Vc. This signal changes the VCO frequency, which is divided by the counter and changes clkDiv according to ƒin.
[pic]
Circuit Diagram
[pic]
Circuit Description
This circuit will function accurately over a 10:1 frequency range from 1 kHz to 10 kHz with the use of the CD4046 frequency detector. When an FIN edge occurs ahead of a F feedback pulse, pin 13 of the CD4046 pulls up on C1 via R1 = 1 kW. This current cannot be controlled or manipulated over as wide a range as “I1” in basic wide range phase locked loop (PLL). As a consequence, the response of this PLL is neither as smooth nor fast-settling as the basic PLL, but it is still better behaved than most F-to-V converters. Show a picture schematic:
Q1 = 2N3565 OR 2N3904 HIGH BETA NPN
A1, A2, A3 = 1/4 LM324
ON CD4046, PINS 1, 2, 4, 6, 7, 10, 11, 12 ARE NO CONNECTION
USE STABLE, LOW-T.C. PARTS FOR COMPONENTS MARKED*
VS = 7 TO 15 VDC
As with the basic PLL, the detector feeds a current to be integrated in C1 (and R2