Principle Of Operation Of N-Channel JFET Case Study

5.2 Principle of Operation of N-Channel JFET:
These are two prerequisites while considering the principle of operation of JFET. Gates are always reverse biased and therefore Gate current IG is practically zero. Source and Drain terminal should be joined together through a voltage source called VDS, drain to source voltage. In an N-channel JFET, source terminal is connected to the negative end of the drain to source supply voltage to send the lectron from source to drain and similarly for an P-channel JFET, source terminal is connected to the positive end of the drain to source supply voltage to send the holes from source to drain.
Let us consider N-channel JFET and discuss its principle of operation for different bias conditions. When VGS
Which ultimately indicates that the for small drain to source voltage, the bulk channel region acts as a constant resistor. The reason behind it is that, VDS being small, the depletion region width across the pn junction is so small that it doesn’t affect in any way the channel width and hence ID increases linearly with VDS.
This ohmic relationship between VDS and ID continues till a critical voltage is reached named pinch-off voltage VPO after which drain current becomes constant and continue with the value IDSS. The term ‘DSS’ indicates the drain(D) to source(S) saturation(S) current when VGS=0.
It should be noted (fig.2b) that under the pinch-off condition channel width becomes minimum at the drain end or the depletion region width becomes maximum at the drain end. Before attaining the pinch off voltage the drain current is maximum (IDSS) through the device and if the voltage is further increased from the pinch-off value, the current from drain to source continues with that value only and remains constant or got saturated. The reason behind this saturation is that, if you increase the VDS further, the immobile ions at the thicker end (Drain end) of the depletion layer repel each other but the depletion region at the source end widens that means the channel length increases. As the depletion region width increases, drain to
At that particular instant VGS can be considered as Vp and the equation ( ) can be rewritten as V_bi-V_P=V_PO or V_P= V_bi-V_PO (4)
Note: gate to source voltage to achieve pinchoff or pinchoff voltage is negative quantity to for n channel JFET.
Similarly,
Figure 3(b) shows the p channel JFET of similar dimension and the induced the space charge layer width h for one sided n+p junction is given by w={(2∈_s (V_bi+V_GS ))/(eN_d )}^(1/2) (5)
For p channel JFET, VGS must be positive to make n+p junction reverse biased. So the internal pinch-off voltage is again can be written as when w=h, we have h={(2∈_s V_PO)/(eN_d )}^(1/2) (6)

V_PO=(eh^2 N_d)/(2∈_s ) (7)
The pinch off voltage for p channel JFET is a positive quantity.
Considering all internal parameter constant, the internal pinch off voltage for a p-channel JFET can be written as when w=h: V_bi+V_P=V_PO or V_P= V_PO-V_bi (8)
Note: gate to source voltage to achieve pinchoff or pinchoff voltage is positive quantity for p channel