Qpsk Modulation
International Journal of Computer Communication and Information System ( IJCCIS) – Vol2. No1. ISSN: 0976–1349 July – Dec 2010
Hardware Implementation of Viterbi Decoder for Wireless Applications
Bhupendra Singh1, Sanjeev Agarwal2 and Tarun Varma3
1
Deptt. of Electronics and Communication Engineering, Amity School of Engineering and Technology, Noida, India Email: 1bsingh.tech@gmail.com 2,3 Malaviya National Institute of Technology, Jaipur, India Email: 2san@mnit.ac.in, 3tarun.varma.jaipur@gmail.com controlled shift register is designed at the circuit level and integrated into the ACS module. A. Structure of Viterbi Decoder The four functional blocks of VD in term of implementation, including branch metric unit (BMU), add-compare-select unit (ACSU), feedback unit (FBU) and survivor memory unit (SMU).
Abstract—In 2G mobile terminals, the VD consumes approximately one third of the power consumption of a baseband mobile transceiver. Thus, in 3G mobile systems, it is essential to reduce the power consumption of the VD. In this report the register exchange (RE) method, adopting a pointer concept, is used to implement the survivor memory unit (SMU) of the VD. For the implementation part, hardware implementation of MLVD through Synopsys Design Compiler Synthesis is done. For synthesis UMC-180nm Library is used. Index Terms— Viterbi Decoder, SMU, ACSU, RE, MLVD I. INTRODUCTION The register exchange (RE) method, adopting a pointer concept, is used to implement the survivor memory unit (SMU) of the VD. The method entails assigning a pointer to each register or memory location. The contents of the pointer, which points to one register, is altered to point to a second register, instead of copying the contents of the first register to the second. When the pointer concept is applied to the RE 's SMU implementation[2], there is no need to copy the contents of the SMU and rewrite them, but one row of memory is still needed for each state of the VD. Thus, the VDs in CDMA
Hardware Implementation of Viterbi Decoder for Wireless Applications
Bhupendra Singh1, Sanjeev Agarwal2 and Tarun Varma3
1
Deptt. of Electronics and Communication Engineering, Amity School of Engineering and Technology, Noida, India Email: 1bsingh.tech@gmail.com 2,3 Malaviya National Institute of Technology, Jaipur, India Email: 2san@mnit.ac.in, 3tarun.varma.jaipur@gmail.com controlled shift register is designed at the circuit level and integrated into the ACS module. A. Structure of Viterbi Decoder The four functional blocks of VD in term of implementation, including branch metric unit (BMU), add-compare-select unit (ACSU), feedback unit (FBU) and survivor memory unit (SMU).
Abstract—In 2G mobile terminals, the VD consumes approximately one third of the power consumption of a baseband mobile transceiver. Thus, in 3G mobile systems, it is essential to reduce the power consumption of the VD. In this report the register exchange (RE) method, adopting a pointer concept, is used to implement the survivor memory unit (SMU) of the VD. For the implementation part, hardware implementation of MLVD through Synopsys Design Compiler Synthesis is done. For synthesis UMC-180nm Library is used. Index Terms— Viterbi Decoder, SMU, ACSU, RE, MLVD I. INTRODUCTION The register exchange (RE) method, adopting a pointer concept, is used to implement the survivor memory unit (SMU) of the VD. The method entails assigning a pointer to each register or memory location. The contents of the pointer, which points to one register, is altered to point to a second register, instead of copying the contents of the first register to the second. When the pointer concept is applied to the RE 's SMU implementation[2], there is no need to copy the contents of the SMU and rewrite them, but one row of memory is still needed for each state of the VD. Thus, the VDs in CDMA
References: [1] Viterbi, "Error bounds for convolutional codes andasymptotically optimum decoding algorithm," IEEE Transactions on Information theory, vol. It-13, no. 2, pp. 260_269, April 1967. Exchange Viterbi Decoder for Low-Power Wireless Communications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 2, pp. 371- 378, February 2004. [2] Dalia A. El-Dib and M.I. Elmasry, “Modified Register- [3] S. B. Wicker, "Error Control Systems for Communication and Storage". Prentice Hall, 1995. vol. 61, no. 3, pp. 268_278, March 1973. Digital [4] G. Forney, “The viterbi algorithm", Proceedings of the IEEE, [5] Dalia A. El-Dib and M.I. Elmasry,”Low power registerexchange Viterbi decoder for high speed wireless communications,” IEEE International Symposium on Circuits and Systems, May 2002, pp. 737-740. [6] S A. El-Dib and M.I. Elmasry, “Memoryless Viterbi Decoder: an extremely low power Viterbi Decoder,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 3, pp. 371- 378, February 2004. 48