Realization of Logic Functions

Realization of logic functions

CMOS monoflops, latches and flipflops

Arithmetic circuits

Buffer circuits

Electronics – Complex CMOS digital circuits
Prof. M´rta Rencz, Gergely Nagy a
BME DED

October 25, 2011

Realization of logic functions

CMOS monoflops, latches and flipflops

Arithmetic circuits

Buffer circuits

CMOS logic
Pull-up network: p-type transistors short circuit, if f (X) = 1 open circuit, if f (X) = 0

Pull-down network: n-type transistors short circuit, if f (X) = 0 open circuit, if f (X) = 1

For example: NOR gate

y = f (X)

Realization of logic functions

CMOS monoflops, latches and flipflops

Arithmetic circuits

Buffer circuits

Complex gates
Complex gates can be realized at transistor level – which is advantageous as the gate delay is smaller for one complex gate than for the series connection of several simple gates realizing the same function. Usually the number of inputs is limited to 4 (the number of transistors in series between the ground and supply is limited). The realized logic function can be any combination of the AND and NOR functions and there is always an inversion at the output: y = (A + B)C y = AB + CD y = (A + B)CD

Realization of logic functions

CMOS monoflops, latches and flipflops

Arithmetic circuits

Buffer circuits

Complex gate design – an example I.
Let’s design the complex gate realizing the logic function y = (A + B)C First the pull-down network (PDN) is created. The OR function is realized by two n-type FETs connected in parallel. The AND function is realized by two n-type FETs connected in series.

Realization of logic functions

CMOS monoflops, latches and flipflops

Arithmetic circuits

Buffer circuits

Complex gate design – an example II.

Next the pull-up network (PUN) is designed with p-type transistors. The PUN has to create a current path between the supply rail and the output for every logic 1 of the logic function. This can be done by creating the dual