Solved Questions on Batching and EOQ
Homework: Batching and EOQ
Operations Management
Instructor: Cuihong Li
Name: Gupta, Randeep
Instruction:
1) Print your name above.
2) Please hand in your work at the beginning of the class on the due date.
3) You need to present not only the answer to each question but also how the answer is reached, for example, the formula, calculation, and explanation when necessary.
4) Total points: 13
1. JCL Inc. is a major chip manufacturing firm that sells its products to computer manufacturers like Dell, HP, and others. In simplified terms, chip making at JCL Inc. involves three basic operations: depositing, patterning, and etching.
Depositing: Using chemical vapor deposition (CVD) technology, an insulating material is deposited on the wafer surface, forming a thin layer of solid material on the chip.
Patterning: Photolithography projects a microscopic circuit pattern on the wafer surface, which has a light-sensitive chemical like the emulsion on photographic film. It is repeated many times as each layer of the chip is built.
Etching: Etching removes selected material from the chip surface to create the device structures. The following table lists the required processing times and setup times at each of the steps. There is unlimited space for buffer inventory between these steps. Assume that the unit of production is a wafer, from which individual chips are cut at a later stage. Note: A Setup can only begin once the batch has arrived at the machine.
Process Step
1 Depositing
2 Patterning
3 Etching
Setup time
0 min.
30 min.
0 min.
Processing time
0.45 min./unit
0.25 min./unit
0.30 min./unit
a. What is the bottleneck step and process capacity (in units per hour) with a batch size of 100 wafers? (2’) Depositing
Patterning
Etching
Capacity
1/0.45 = 2.2222 100/(100*0.25 + 30) = 1.8182 1/0.30 = 3.3333
Capacity (Units/Hr)
133.33
109.09
200
Bottleneck step = Patterning.
b. What is the bottleneck step and process capacity (in units per hour) with a batch size of
Operations Management
Instructor: Cuihong Li
Name: Gupta, Randeep
Instruction:
1) Print your name above.
2) Please hand in your work at the beginning of the class on the due date.
3) You need to present not only the answer to each question but also how the answer is reached, for example, the formula, calculation, and explanation when necessary.
4) Total points: 13
1. JCL Inc. is a major chip manufacturing firm that sells its products to computer manufacturers like Dell, HP, and others. In simplified terms, chip making at JCL Inc. involves three basic operations: depositing, patterning, and etching.
Depositing: Using chemical vapor deposition (CVD) technology, an insulating material is deposited on the wafer surface, forming a thin layer of solid material on the chip.
Patterning: Photolithography projects a microscopic circuit pattern on the wafer surface, which has a light-sensitive chemical like the emulsion on photographic film. It is repeated many times as each layer of the chip is built.
Etching: Etching removes selected material from the chip surface to create the device structures. The following table lists the required processing times and setup times at each of the steps. There is unlimited space for buffer inventory between these steps. Assume that the unit of production is a wafer, from which individual chips are cut at a later stage. Note: A Setup can only begin once the batch has arrived at the machine.
Process Step
1 Depositing
2 Patterning
3 Etching
Setup time
0 min.
30 min.
0 min.
Processing time
0.45 min./unit
0.25 min./unit
0.30 min./unit
a. What is the bottleneck step and process capacity (in units per hour) with a batch size of 100 wafers? (2’) Depositing
Patterning
Etching
Capacity
1/0.45 = 2.2222 100/(100*0.25 + 30) = 1.8182 1/0.30 = 3.3333
Capacity (Units/Hr)
133.33
109.09
200
Bottleneck step = Patterning.
b. What is the bottleneck step and process capacity (in units per hour) with a batch size of