CMIS 310
UMUC
Abstract
Since the invention of the first computer, engineers have been conceptualizing and implementing ways to optimize system performance. The last 25 years have seen a rapid evolution of many of these concepts, particularly cache memory, virtual memory, pipelining, and reduced set instruction computing (RISC). Individual each one of these concepts has helped to increase speed and efficiency thus enhancing overall system performance. Most systems today make use of many, if not all of these concepts. Arguments can be made to support the importance of any one of these concepts over one another, however, the use of cache memory or “caching” has been one of the most efficient and effective methods to increase system performance.
Introduction
Over the past 25 years, there has been much advancement in computer systems and architecture to improve system performance. The development of concepts such as cache memory, virtual memory, pipelining, and reduced instruction set computing (RISC) have led to increases in speed and processing power, as well as optimization of CPU usage and energy efficiency. These concepts have evolved over the years, and continue to evolve and give rise to new concepts which enhance system performance at an almost exponential rate. Computers today are more powerful, and cheaper to manufacture and maintain than ever before. This paper will examine the evolution of, and current trends in improving computer system performance by exploring concepts such as cache memory, virtual memory, pipelining, and RISC, and assessing the impact these concepts have made, and continue to make on system performance.
Cache Memory
The invention of the microprocessor allowed computers to become smaller and faster than ever before by drastically shrinking the size of the central processing unit (CPU). At the
References: Alameldeen, A., Kim, N., Khan, S. Ghasemi, H. Wilkerson, C., Kulkarni, J. & Jimenez, D. (2013). Chen, C., Novick, G., & Shimano, K. (2006). RISC Architecture. Retrieved October 9, 2014 from http://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/ Davis, R. (2005, November 22). Microprocessor History. Tech-tips. Retrieved October 8, 2014 from http://www.geeks.com/techtips/2005/techtips-NOV22-05.htm. Denning, P. (2012, July 1). Virtual Memory. CRC Handbook of Computer Science and Engineering. Retrieved October 8, 2014 from http://denninginstitute.com/pjd/PUBS/ENC/CRC-vm-2012.pdf. Ibrahim, M. (2009, February 1). How Pipelining Improves CPU Performance. Digital Internals. Retrieved October 8, 2014 from http://www.digitalinternals.com/hardware/how-pipelining-improves-cpu-performance/113/. Lemley, B., Bascar T., & Kim, K. Virtual Memory. (1999). The Core of Information Technology. George Mason University Mahad, F., Wan-kadir, W., (2013, June 30). IMPROVING WEB SERVER PERFORMANCE USING TWO-TIERED WEB CACHING Mann, D. (1992, November 2). Speed system operation by matching CPU to need: understanding the many forms of context switching is the key to maximizing RISC performance in embedded-system applications Nass, R. (1991, March 28). RISC platforms iron out price/performance kinks. Electronic Design Torres, G. (2007, September 12). How The Memory Cache Works. Hardware Secrets. Retrieved October 8, 2014 from http://www.hardwaresecrets.com/article/How-The-Memory-Cache-Works/481/3. Weaver, C., Barr, K. Marsman, E. Ernst, D. & Austin, T. (2001). Performance Analysis Using Pipeline Visualization