Time to Digital Converter Used in All Digital Pll
Master Thesis ICT
Time to Digital Converter used in ALL digital PLL
Master of Science Thesis In System-on-Chip Design By Chen Yao Stockholm, 08, 2011
Supervisor: Dr. Fredrik Jonsson and Dr. Jian Chen Examiner: Prof. Li-Rong Zheng
Master Thesis TRITA-ICT-EX-2011:212
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ACKNOWLEDGEMENTS
I would like to thank: Professor Li-Rong Zheng for giving me the opportunity to do my master thesis project in IPACK group at KTH. Dr. Fredrik Jonsson for providing me with the interesting topic and guiding me for the overall research and plan. Dr. Jian Chen for answering all my questions and making the completion of the project possible. Geng Yang, Liang Rong, Jue Shen, Xiao-Hong Sun in IPACK group for the discussion and valuable suggestions during the thesis work. My mother Xiu-Yun Zheng and my husband Ming-Li Cui for always supporting and encouraging me.
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ABSTRACT
This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters. Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442µW with 1.2V power supply. Measured integral nonlinearity and differential nonlinearity are 0.5LSB and 0.33LSB respectively. Keywords: All Digital PLL, Time to Digital Converter (TDC), Sensed Amplifier Flip Flop (SAFF), Current Starved, Vernier delay line
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Contents
ACKNOWLEDGEMENTS
Time to Digital Converter used in ALL digital PLL
Master of Science Thesis In System-on-Chip Design By Chen Yao Stockholm, 08, 2011
Supervisor: Dr. Fredrik Jonsson and Dr. Jian Chen Examiner: Prof. Li-Rong Zheng
Master Thesis TRITA-ICT-EX-2011:212
1
ACKNOWLEDGEMENTS
I would like to thank: Professor Li-Rong Zheng for giving me the opportunity to do my master thesis project in IPACK group at KTH. Dr. Fredrik Jonsson for providing me with the interesting topic and guiding me for the overall research and plan. Dr. Jian Chen for answering all my questions and making the completion of the project possible. Geng Yang, Liang Rong, Jue Shen, Xiao-Hong Sun in IPACK group for the discussion and valuable suggestions during the thesis work. My mother Xiu-Yun Zheng and my husband Ming-Li Cui for always supporting and encouraging me.
i
ABSTRACT
This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters. Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442µW with 1.2V power supply. Measured integral nonlinearity and differential nonlinearity are 0.5LSB and 0.33LSB respectively. Keywords: All Digital PLL, Time to Digital Converter (TDC), Sensed Amplifier Flip Flop (SAFF), Current Starved, Vernier delay line
ii
Contents
ACKNOWLEDGEMENTS