Vhdl Coding Style for Digital Design
1 Application Notes
Infineon technologies Chapter
1
VHDL Coding Guidelines
SC Highway Release 2.1, June 26, 2000
Application Notes
1
VHDL Coding Guidelines
Infineon technologies 1.1
Introduction
Coding of design behaviour and architecture is one of the most important steps in the whole chip design project. It has major impact on logic synthesis and routing results, timing robustness, verifiability, testability and even product support. The VHDL Coding Guidelines help chip and macro development teams to rapidly understand each other's code. Macro based designs integrate easier, if these common coding styles are followed. This also applies to externally developed softcores. Codes will not need modification if simulator, synthesis tool or technology is exchanged. Code invariance wrt. Synthesis tool is given in case of a similar VHDL synthesis subset. Code invariance wrt. technology is given in case of similar performance and cell set. In addition the given guidelines enable high synthesis quality and simulation performance. The VHDL Coding Guidelines need continuous adaptation according to new tool properties and new upcoming methodologies. Please participate in this process with your design know-how. Direct your contributions and related questions to the SC Highway Frontend Hotline (hwfe@hl.siemens.de, tel.: 24666). Contribute rules for VHDL coding, that turned out to prevent errors in the downstream flow, or recommendations, that alleviate further design, re-use or maintenance. The VHDL Coding Guidelines may be passed to sub-contractors or cooperation partners. Ideally their coding works should comply to these guidelines, enabling rapid and safe integration with internally developed modules. Reading of the VHDL Coding Guidelines is most efficient at the beginning of a chip-design-project. Furthermore "Early Code Review" should be considered in a very early phase of VHDL coding as a training measure. Up to now every designer is
Infineon technologies Chapter
1
VHDL Coding Guidelines
SC Highway Release 2.1, June 26, 2000
Application Notes
1
VHDL Coding Guidelines
Infineon technologies 1.1
Introduction
Coding of design behaviour and architecture is one of the most important steps in the whole chip design project. It has major impact on logic synthesis and routing results, timing robustness, verifiability, testability and even product support. The VHDL Coding Guidelines help chip and macro development teams to rapidly understand each other's code. Macro based designs integrate easier, if these common coding styles are followed. This also applies to externally developed softcores. Codes will not need modification if simulator, synthesis tool or technology is exchanged. Code invariance wrt. Synthesis tool is given in case of a similar VHDL synthesis subset. Code invariance wrt. technology is given in case of similar performance and cell set. In addition the given guidelines enable high synthesis quality and simulation performance. The VHDL Coding Guidelines need continuous adaptation according to new tool properties and new upcoming methodologies. Please participate in this process with your design know-how. Direct your contributions and related questions to the SC Highway Frontend Hotline (hwfe@hl.siemens.de, tel.: 24666). Contribute rules for VHDL coding, that turned out to prevent errors in the downstream flow, or recommendations, that alleviate further design, re-use or maintenance. The VHDL Coding Guidelines may be passed to sub-contractors or cooperation partners. Ideally their coding works should comply to these guidelines, enabling rapid and safe integration with internally developed modules. Reading of the VHDL Coding Guidelines is most efficient at the beginning of a chip-design-project. Furthermore "Early Code Review" should be considered in a very early phase of VHDL coding as a training measure. Up to now every designer is