Vlsi Based Accident Information and Car Security Systemabstract: Vlsi Based Accident Information and Car Security System

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 4, APRIL 2012

Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling
Avesta Sasan, Member, IEEE, Kiarash Amiri, Student Member, IEEE, Houman Homayoun, Member, IEEE, Ahmed M. Eltawil, Member, IEEE, and Fadi J. Kurdahi, Fellow, IEEE

Abstract—In this paper we present the “Variation Trained Drowsy Cache” (VTD-Cache) architecture. VTD-Cache allows for a significant reduction in power consumption while addressing reliability issues raised by memory cell process variability. By managing voltage scaling at a very fine granularity, each cache way can be sourced at a different voltage where the selection of voltage levels depends on both the vulnerability of the memory cells in that cache way to process variation and the likelihood of access to that cache location. After a short training period, the proposed architecture will micro-tune the cache, allowing significant power reduction with negligible increase in the number of misses. In addition, the proposed architecture actively monitors the access pattern and reconfigures the supply voltage setting to adapt to the execution pattern of the program. The novel and modular architecture of the VTD-Cache and its associated controller makes it easy to be implemented in memory compilers with a small area and power overhead. In a case study, the SimpleScalar simulation of the proposed 32 kB cache architecture reports over 57% reduction in power consumption over standard SPEC2000 integer benchmarks while incurring an area overhead of less than 4% and an execution time penalty smaller than 1%. Index Terms—Cache, drowsy cache, fault tolerance, leakage, low power, manufacturing defects, power efficient, process variation, static random access memory (SRAM), technology scaling, voltage scaling.

I. INTRODUCTION

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ECENT studies [1]–[3] suggest that static power consumption is

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[28] R. K. Krishnarnurthy, A. Alvandpour, V. De, and S. Borkar, “High-performance and low-power challenges for sub-70 nm microprocessor circuits,” in Proc. IEEE Custom Integr. Circuits Conf., 2002, pp. 125–128. [29] K. Kuhn, “32nm SOC process, getting many things right at once,” Mar. 26, 2010. [Online]. Available: http://blogs.intel.com/technology/ 2010/03/32nm_soc_process_an_analogy_wi.php Avesta Sasan (Mohammad A. Makhzan) (M’05) received the B.S. degree (summa cum laude) in computer engineering and the M.S. and Ph.D. degrees in electrical engineering from University of California Irvine, Irvine, in 2005, 2006, and 2010, respectively. He is currently with Broadcom Corporation. His research interests include low power design, process variation aware architectures, fault tolerant computing systems, nano-electronic power and device modeling, VLSI signal processing, processor power and reliability optimization and logic-architecture-device co-design. His latest publication and research updates can be found on http://www.avestasasan.com. Kiarash Amiri (S’10) received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 2003, and the M.Sc. degree in electrical engineering from University of Southern California, Los Angeles, in 2006. He is currently pursuing the Ph.D. degree in electrical engineering from the Department of Electrical Engineering and Computer Science, University of California, Irvine. His research interests include multimedia data compression, low power video and image coding, process variation aware system design, and fault tolerant computing. Houman Homayoun (M’04) received the B.S. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 2003, the M.S. degree in computer engineering from University of Victoria, Canada, in 2005, and the Ph.D. degree in computer science from University of California, Irvine, Irvine, in 2010. Dr. Homayoun was the recipient of the four-years UCI/ICS chair fellowship. His research interests include power-temperature and reliability-aware memory and processor design optimizations and spans the areas of computer architecture and VLSI circuit design. The results of his research were published in top-rated conferences including ISLPED, DAC, DATE, HiPEAC, CASES, ICCD, CF, and LCTES. 642 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 4, APRIL 2012 Ahmed M. Eltawil (M’97) received the Doctorate degree from the University of California, Los Angeles, in 2003 and the M.Sc. and B.Sc. degrees (with honors) from Cairo University, Giza, Egypt, in 1999 and 1997, respectively. He is an Associate Professor with the University of California, Irvine, where he has been with the Department of Electrical Engineering and Computer Science, University of California, Irvine, since 2005. He is the founder and director of the Wireless Systems and Circuits Laboratory (http://newport.eecs.uci.edu/ ~aeltawil/), a member laboratory of the Center for Pervasive Communications and Computing (CPCC). He also holds a visiting professorship with King Saud University, Saudi Arabia. His current research interests include low power digital circuit and signal processing architectures for wireless communication systems with a focus on physical layer design where he has published over 60 technical papers on the subject, including four book chapters. Dr. Eltawil has been on the technical program committees for numerous workshops, symposia, and conferences in the area of VLSI and communication system design. He has received several distinguished awards, including the NSF CAREER Award in 2010 supporting his research in low power systems, as well as the Best Paper Award in 2006 at ISQED. Since 2006, he has been a member of the Association of Public Safety Communications Officials (APCO) and has been actively involved in efforts towards integrating cognitive and software defined radio technology in critical first responder communication networks. Fadi J. Kurdahi (M’87–SM’03–F’05) received the Ph.D. degree from the University of Southern California, Los Angeles, in 1987. Since then, he has been a faculty member with the Department of Electrical and Computer Engineering, University of California, Irvine (UCI), where he conducts research in the areas of computer-aided design of VLSI circuits, high-level synthesis, and design methodology of large scale systems, and serves as the Associate Director for the Center for Embedded Computer Systems (CECS). Dr. Kurdahi was an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, Area Editor in IEEE Design and Test for reconfigurable computing, and served as program chair, general chair, or on program committees of several workshops, symposia, and conferences in the area of CAD, VLSI, and system design. He was a recipient of the Best Paper Award for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS in 2002, the Best Paper Award in 2006 at ISQED, and four other Distinguished Paper Awards at DAC, EuroDAC, ASP- DAC, and ISQED. He also received the Distinguished Alumnus Award from this Alma Mater, the American University of Beirut in 2008. He is a fellow of the AAAS.