Vlsi Implementation of Serial-Serial Multiplier Based on Asynchronous Counter Accumulation
International Conference on Computing and Control Engineering (ICCCE 2012), 12 & 13 April, 2012
VLSI Implementation of Serial-Serial Multiplier based on Asynchronous Counter Accumulation
Y. Arun Benjamin Francis
Abstract—Multipliers are the fundamental and essential building blocks of VLSI systems. The design and implementation approaches of multipliers contribute substantially to the area, speed and power consumption of computation intensive VLSI system. The objective of the project is to design for applications with high data sampling rate.
In the multiplier the partial product are effective ly formed by the dependency graph so that for an nxn multiplication the number of sampling cycles reduced from 2n to n. The full adder in the conventional multiplier is replaced by asynchronous counters so that the critical path is limited to only one AND gate.
Keywords—Very large scale integration, asynchronous counter.
I. INTRODUCTION
S
ERIAL multipliers are popular for their low area and power, and are more suitable for bit -serial signal processing applications with I/O constraints and on -chip serial-link bus architectures. Often, the delay of multipliers dominates the critical path of these systems and due to issues concerning reliability and portability, power consumption is a critical criterion for applications that demand low-power as its primary metric. While low power and high speed multiplier circuits are highly demanded, it is not always possible to achieve both criteria simultaneously. Therefore, a good multiplier design requires some tradeoff between speed and power consumption
II. REVIEW OF SERIAL MULTIPLIERS
multiplier that is modular in structure and can operate on both signed and unsigned numbers. The 1-bit slice of a typical serial-serial multiplier, called a bit-cell (BC), is excerpted from is shown . Such cells are interconnected to produce the output in a bit-serial manner for an serial-serial multiplier. The
VLSI Implementation of Serial-Serial Multiplier based on Asynchronous Counter Accumulation
Y. Arun Benjamin Francis
Abstract—Multipliers are the fundamental and essential building blocks of VLSI systems. The design and implementation approaches of multipliers contribute substantially to the area, speed and power consumption of computation intensive VLSI system. The objective of the project is to design for applications with high data sampling rate.
In the multiplier the partial product are effective ly formed by the dependency graph so that for an nxn multiplication the number of sampling cycles reduced from 2n to n. The full adder in the conventional multiplier is replaced by asynchronous counters so that the critical path is limited to only one AND gate.
Keywords—Very large scale integration, asynchronous counter.
I. INTRODUCTION
S
ERIAL multipliers are popular for their low area and power, and are more suitable for bit -serial signal processing applications with I/O constraints and on -chip serial-link bus architectures. Often, the delay of multipliers dominates the critical path of these systems and due to issues concerning reliability and portability, power consumption is a critical criterion for applications that demand low-power as its primary metric. While low power and high speed multiplier circuits are highly demanded, it is not always possible to achieve both criteria simultaneously. Therefore, a good multiplier design requires some tradeoff between speed and power consumption
II. REVIEW OF SERIAL MULTIPLIERS
multiplier that is modular in structure and can operate on both signed and unsigned numbers. The 1-bit slice of a typical serial-serial multiplier, called a bit-cell (BC), is excerpted from is shown . Such cells are interconnected to produce the output in a bit-serial manner for an serial-serial multiplier. The
References: Des. (ICCAD), San Jose, CA, 2008, pp. 11 –18. 5, pp.447–452, Oct. 2006.