Analysis Of AMBA-Based Microcontroller

AMBA products:
A family of synthesizable intellectual property (IP) cores, AMBA Products licensable from ARM Limited that implement a digital highway in a SoC (System On Chip) for the efficient moving, for high performance, high clock frequency and storing of data using the AMBA protocol qualifications. The AMBA family includes AMBA Network Interconnect (NIC-301), SDRAM, FLASH memory controllers (DMC-34x, SMC-35x), DMA controllers (DMA-230, DMA-330), level 2 cache controllers (L2C-310), etc
A typical AMBA-based microcontroller:
An AMBA-based microcontroller typically consists of a high-performance system backbone bus (AMBA AHB or AMBA ASB), able to sustain the outside
Each channel uses the similar trivial handshaking between source and destination (master or slave, depending happening channel path), which simplifies the interface design.
Unlike AHB concept is not an afterthought but is the central focus of the protocol design. In AXI3 all connections are bursts of lengths between 1 and 16. The addition of byte allow signals for the data bus supports unaligned memory accesses and store merging.
The communication between master and slave is transaction-oriented, where each contract consists of address, data, and reply transfers on their corresponding channels. Apart starting rather liberal ordering rules there is no strict protocol-enforced timing relation between individual phases of a transaction. Instead each transfer identifies itself as part of a specific transaction by its transaction ID tag. Transactions may entire out-of-order and transfers belonging to different transactions may be interleaved. Thanks to the ID that each transfer carries, out-of-order transactions can be sorted out at destination.

III. PROPOSED
FIFO: FIFO (first in, first out) is the memory which is used as the slave in this project. Input is taken from the AXI-BUS as the data-input and the corresponding information or data is stored in the FIFO memory.
ROM:
ROM (Read only memory) is the memory which is used as the slave in this project. Input is taken from the AXI-BUS as the data-input and the corresponding information or data is taken as the address line, the data in that address line which is stored initially that data is taken as the Rom output because ROM is just a reads data.
SRAM:
SRAM (static random access memory) is the memory which is used as the slave in this project. Input is taken from the AXI-BUS as the data-input and the corresponding information or data is stored in the SRAM memory.