cmos

CHAPTER

5

THE CMOS INVERTER
Quantification of integrity, performance, and energy metrics of an inverter
Optimization of an inverter design

5.1

Exercises and Design Problems

5.4.2

5.2

The Static CMOS Inverter — An Intuitive
Perspective

Propagation Delay: First-Order
Analysis

5.4.3

Propagation Delay from a Design
Perspective

5.3

Evaluating the Robustness of the CMOS
Inverter: The Static Behavior

5.5

Power, Energy, and Energy-Delay

5.3.1

Switching Threshold

5.5.1

Dynamic Power Consumption

5.3.2

Noise Margins

5.5.2

Static Consumption

Robustness Revisited

5.5.3

Putting It All Together

5.5.4

Analyzing Power Consumption Using
SPICE

5.3.3
5.4

Performance of CMOS Inverter: The Dynamic
Behavior
5.4.1

180

Computing the Capacitances

5.6

Perspective: Technology Scaling and its
Impact on the Inverter Metrics

Section 5.1

181

Exercises and Design Problems
1.

[M, SPICE, 3.3.2] The layout of a static CMOS inverter is given in Figure 5.1. (λ = 0.125 µm). a. Determine the sizes of the NMOS and PMOS transistors.
b. Plot the VTC (using HSPICE) and derive its parameters (VOH, VOL, VM, VIH, and VIL).
c. Is the VTC affected when the output of the gates is connected to the inputs of 4 similar gates?. GND

Poly

In
VDD = 2.5 V.
Poly

2λ

5.1

Exercises and Design Problems

PMOS

NMOS
Metal1
Out
Metal1

Figure 5.1

2.

CMOS inverter layout.

d. Resize the inverter to achieve a switching threshold of approximately 0.75 V. Do not layout the new inverter, use HSPICE for your simulations. How are the noise margins affected by this modification?
Figure 5.2 shows a piecewise linear approximation for the VTC. The transition region is approximated by a straight line with a slope equal to the inverter gain at VM. The intersection of this line with the VOH and the VOL lines defines VIH and VIL.
a. The noise margins of a CMOS inverter are