Ewh Layout
COMP32212 Implementing System-on-Chip Designs
School of Computer Science
Lecture Outline
• Verification • CMOS Technology • Layout • Reliability • Future of CMOS http://www.cs.manchester.ac.uk/Study_subweb/Ugrad/coursenotes/COMP32212/ 1
1
COMP32212 Implementing System-on-Chip Designs
School of Computer Science
Lecture 10 LAYOUT Lecture aims • to understand the requirements for design rules • to translate simple circuit designs to layout • to appreciate different layout styles • complex gate layout • standard cell layout
2
The main aims of this lecture are to understand how we can abstract away the detailed requirements for IC layout and produce a standard set of design rules which when used in conjunction with the abstracted layout can generate a full set of masks for IC fabrication. We will also look at a range of layout styles appropriate for generating more generalised layouts such as those required for producing standard cell libraries..
2
COMP32212 Implementing System-on-Chip Designs
School of Computer Science
Layout Design Rules
• Designs are represented by geometries on specific layers • Each layer in the layout represents a process during manufacture • Design rules set the limitations on the layout geometries • They are a consequence of the methods used to manufacture the devices
3
We will now look at the layout of our devices in more detail and look at how we can develop a set of scaleable design rules. We represent the stages in manufacture as a set of layers in the design process. Each layer has a set of geometries (polygons etc) which represent the features to be reproduced at that stage of the process. It is clear that we must have a set of minimum feature sizes for each layer and a set of values for minimum spacing between features on each layer and between features on different layers. These are our layout design rules. The values for these minimum sizes depend on the particular process being used to
School of Computer Science
Lecture Outline
• Verification • CMOS Technology • Layout • Reliability • Future of CMOS http://www.cs.manchester.ac.uk/Study_subweb/Ugrad/coursenotes/COMP32212/ 1
1
COMP32212 Implementing System-on-Chip Designs
School of Computer Science
Lecture 10 LAYOUT Lecture aims • to understand the requirements for design rules • to translate simple circuit designs to layout • to appreciate different layout styles • complex gate layout • standard cell layout
2
The main aims of this lecture are to understand how we can abstract away the detailed requirements for IC layout and produce a standard set of design rules which when used in conjunction with the abstracted layout can generate a full set of masks for IC fabrication. We will also look at a range of layout styles appropriate for generating more generalised layouts such as those required for producing standard cell libraries..
2
COMP32212 Implementing System-on-Chip Designs
School of Computer Science
Layout Design Rules
• Designs are represented by geometries on specific layers • Each layer in the layout represents a process during manufacture • Design rules set the limitations on the layout geometries • They are a consequence of the methods used to manufacture the devices
3
We will now look at the layout of our devices in more detail and look at how we can develop a set of scaleable design rules. We represent the stages in manufacture as a set of layers in the design process. Each layer has a set of geometries (polygons etc) which represent the features to be reproduced at that stage of the process. It is clear that we must have a set of minimum feature sizes for each layer and a set of values for minimum spacing between features on each layer and between features on different layers. These are our layout design rules. The values for these minimum sizes depend on the particular process being used to