Hybrid Nano Memristor/CMOS Architecture Analysis
Fig. 3 The hybrid Nano Memristor/CMOS architecture [23].
This hybrid Nano/CMOS architecture is showing great promises in Spin-Transfer Torque Magnetic RAM (STT-MRAM), which is well suited for many mainstream applications, especially memory storage devices [26, 27, 25, and 28]. By utilizing this architecture in this application, the size and the speed of this technology would be improved greatly. In addition, the read and write time for these architectures is nearly 120 picoseconds [29, 30]. The only problem with Memristors is that they are capable of being rewritten about 1010 [31], but recently there has been some new researches which showed that it is possible to increase the endurance limitation of Memristors to at least 1015 [32]. This …show more content…
This means that a huge layout area is necessary for this design.
In [36], the authors have design new full adder that its baseline (for 1-bit full adder) requires 4 Memristors, 5 resistors, 13 switches and 4 drivers. This architecture is shown in figure 6.
Fig. 6 The utilized1-bit Memristor-Based full adder in [36].
Although the output is driven out only by three steps, because of the resistances and the drivers the full adder proposed in [36] suffers from a large lay out area and huge power consumption.
In [37], the authors have used hybrid Nano Memristor/CMOS architecture in their designs, which are shown in figures 7-9. Figure 7 shows the operation to accumulate the intermediate Sum. Then, the intermediate and final Carry-out are calculated in figure 8 and 9, respectively. Finally, the Sum is accumulated by using the same architecture similar to the one shown in figure 7.
Fig. 7 The proposed Memristor-Based 1 bit full adder (accumulating Intermediate Sum) [37].
Fig. 8 The utilized 1-bit Memristor-Based full adder (accumulating intermediate carry) in [37].
Fig. 9 The utilized 1-bit Memristor-Based full adder (accumulating final Carry-out) in …show more content…
The following rules are also driven out by checking the truth table for each and every one of them. Their proof lies within table 1 (Part 1 to Part 3)
(p IMP q ̅ ) IMP q ̅==(p ̅ IMP q) IMP p==q IMP p (13)
(p IMP q ̅ ) IMP p ̅==(p ̅ IMP q) IMP q==p IMP q (14) p ̅ IMP q==q ̅ IMP p (OR Gate in Boolean logic) (15) p IMP q ̅==q IMP p ̅ (NAND Gate in Boolean logic) (16)
¯(p ̅ IMP q)==¯(q ̅ IMP p) (NOR Gate in Boolean logic) (17)
¯(p IMP q ̅ )==¯(q IMP p ̅ ) (AND Gate in Boolean logic) (18) p IMP (q IMP z)==q IMP (p IMP z) (19)
(p IMP q ̅) IMP p ̅==(p ̅ IMP q) IMP q (20)
(p IMP q)IMP ¯((p ̅ IMP q ̅ ) ) (XOR Gate in Boolean logic) (21)
(p IMP q)IMP ¯((q IMP p) )(XOR Gate in Boolean logic) (22)
¯((p ̅ IMP q) IMP ¯((p IMP q ̅)))(XOR Gate in Boolean logic) (23)
(p IMP q ̅ )IMP ¯((p ̅ IMP q) ) (XNOR Gate in Boolean logic) (24)
(z IMP p ̅) IMP ¯((z IMP q ̅ )) (MUX in Boolean logic)
This hybrid Nano/CMOS architecture is showing great promises in Spin-Transfer Torque Magnetic RAM (STT-MRAM), which is well suited for many mainstream applications, especially memory storage devices [26, 27, 25, and 28]. By utilizing this architecture in this application, the size and the speed of this technology would be improved greatly. In addition, the read and write time for these architectures is nearly 120 picoseconds [29, 30]. The only problem with Memristors is that they are capable of being rewritten about 1010 [31], but recently there has been some new researches which showed that it is possible to increase the endurance limitation of Memristors to at least 1015 [32]. This …show more content…
This means that a huge layout area is necessary for this design.
In [36], the authors have design new full adder that its baseline (for 1-bit full adder) requires 4 Memristors, 5 resistors, 13 switches and 4 drivers. This architecture is shown in figure 6.
Fig. 6 The utilized1-bit Memristor-Based full adder in [36].
Although the output is driven out only by three steps, because of the resistances and the drivers the full adder proposed in [36] suffers from a large lay out area and huge power consumption.
In [37], the authors have used hybrid Nano Memristor/CMOS architecture in their designs, which are shown in figures 7-9. Figure 7 shows the operation to accumulate the intermediate Sum. Then, the intermediate and final Carry-out are calculated in figure 8 and 9, respectively. Finally, the Sum is accumulated by using the same architecture similar to the one shown in figure 7.
Fig. 7 The proposed Memristor-Based 1 bit full adder (accumulating Intermediate Sum) [37].
Fig. 8 The utilized 1-bit Memristor-Based full adder (accumulating intermediate carry) in [37].
Fig. 9 The utilized 1-bit Memristor-Based full adder (accumulating final Carry-out) in …show more content…
The following rules are also driven out by checking the truth table for each and every one of them. Their proof lies within table 1 (Part 1 to Part 3)
(p IMP q ̅ ) IMP q ̅==(p ̅ IMP q) IMP p==q IMP p (13)
(p IMP q ̅ ) IMP p ̅==(p ̅ IMP q) IMP q==p IMP q (14) p ̅ IMP q==q ̅ IMP p (OR Gate in Boolean logic) (15) p IMP q ̅==q IMP p ̅ (NAND Gate in Boolean logic) (16)
¯(p ̅ IMP q)==¯(q ̅ IMP p) (NOR Gate in Boolean logic) (17)
¯(p IMP q ̅ )==¯(q IMP p ̅ ) (AND Gate in Boolean logic) (18) p IMP (q IMP z)==q IMP (p IMP z) (19)
(p IMP q ̅) IMP p ̅==(p ̅ IMP q) IMP q (20)
(p IMP q)IMP ¯((p ̅ IMP q ̅ ) ) (XOR Gate in Boolean logic) (21)
(p IMP q)IMP ¯((q IMP p) )(XOR Gate in Boolean logic) (22)
¯((p ̅ IMP q) IMP ¯((p IMP q ̅)))(XOR Gate in Boolean logic) (23)
(p IMP q ̅ )IMP ¯((p ̅ IMP q) ) (XNOR Gate in Boolean logic) (24)
(z IMP p ̅) IMP ¯((z IMP q ̅ )) (MUX in Boolean logic)