microprogram sequencer
Microprogram sequencer
US 4370729 A
ABSTRACT
A microprogram sequencer for generating in a proper sequence the addresses of the successive microinstructions used in executing a given machine instruction includes a PROM next address generator that produces the successive addresses. The successive addresses are utilized as the successive microinstructions. Each address produced includes a normal next address, but this normal next address may be alterable by address alteration signals that are generated in response to a number of sensed conditions within the computer and in response to predetermined machine instruction register bits. The address alteration of a normal next address, if required, is accomplished within the same clock period in which the normal next address is initially formed, permitting jump or branch instructions to be performed as rapidly as normal instructions. No mapping PROM, microsequencer counter, nor microsequencer incrementer are needed to implement the present invention.
IMAGES(6)
CLAIMS(7)
What is claimed is:
1. A microprogram sequencer for generating in a proper sequence, including required branching, the addresses of the successive microinstructions used in executing a given machine instruction by a computer of the type in which status signals are produced which represent the status of various components of the computer, and in which the operation of the various components is synchronized by a clock which generates a periodic clock signal demarking successively occurring machine cycle clock periods, said microprogram sequencer comprising in combination: address generator memory means for producing during a current machine cycle period a first set of output signals including a first code set of signals designating a normal next input address for said address generator memory means; selector means receiving as inputs applied status signals, instruction signals, and predetermined ones of the set of
US 4370729 A
ABSTRACT
A microprogram sequencer for generating in a proper sequence the addresses of the successive microinstructions used in executing a given machine instruction includes a PROM next address generator that produces the successive addresses. The successive addresses are utilized as the successive microinstructions. Each address produced includes a normal next address, but this normal next address may be alterable by address alteration signals that are generated in response to a number of sensed conditions within the computer and in response to predetermined machine instruction register bits. The address alteration of a normal next address, if required, is accomplished within the same clock period in which the normal next address is initially formed, permitting jump or branch instructions to be performed as rapidly as normal instructions. No mapping PROM, microsequencer counter, nor microsequencer incrementer are needed to implement the present invention.
IMAGES(6)
CLAIMS(7)
What is claimed is:
1. A microprogram sequencer for generating in a proper sequence, including required branching, the addresses of the successive microinstructions used in executing a given machine instruction by a computer of the type in which status signals are produced which represent the status of various components of the computer, and in which the operation of the various components is synchronized by a clock which generates a periodic clock signal demarking successively occurring machine cycle clock periods, said microprogram sequencer comprising in combination: address generator memory means for producing during a current machine cycle period a first set of output signals including a first code set of signals designating a normal next input address for said address generator memory means; selector means receiving as inputs applied status signals, instruction signals, and predetermined ones of the set of