Uart
Section 47. Interrupts (Part V)
HIGHLIGHTS
This section of the manual contains the following major topics: 47.1 47.2 47.3 47.4 47.5 47.6 47.7 47.8 47.9 Introduction .................................................................................................................. 47-2 Non-Maskable Traps.................................................................................................... 47-7 Interrupt Processing Timing ....................................................................................... 47-12 Interrupt Control and Status Registers....................................................................... 47-15 Interrupt Setup Procedures........................................................................................ 47-65 Register Maps............................................................................................................ 47-68 Design Tips ................................................................................................................ 47-70 Related Application Notes.......................................................................................... 47-71 Revision History ......................................................................................................... 47-72
47
Interrupts (Part V)
© 2009 Microchip Technology Inc.
Preliminary
DS70597A-page 47-1
dsPIC33F Family Reference Manual
47.1 INTRODUCTION
The dsPIC33F Interrupt Controller module reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33F CPU. Following are the module features: • • • • • • • Up to eight processor exceptions and software traps Seven user-selectable priority levels Interrupt Vector Table (IVT) with up to 126 vectors Unique vector for each interrupt or exception source Fixed priority within a specified user priority level Alternate Interrupt Vector Table (AIVT) for debugging support Fixed interrupt entry and return latencies
HIGHLIGHTS
This section of the manual contains the following major topics: 47.1 47.2 47.3 47.4 47.5 47.6 47.7 47.8 47.9 Introduction .................................................................................................................. 47-2 Non-Maskable Traps.................................................................................................... 47-7 Interrupt Processing Timing ....................................................................................... 47-12 Interrupt Control and Status Registers....................................................................... 47-15 Interrupt Setup Procedures........................................................................................ 47-65 Register Maps............................................................................................................ 47-68 Design Tips ................................................................................................................ 47-70 Related Application Notes.......................................................................................... 47-71 Revision History ......................................................................................................... 47-72
47
Interrupts (Part V)
© 2009 Microchip Technology Inc.
Preliminary
DS70597A-page 47-1
dsPIC33F Family Reference Manual
47.1 INTRODUCTION
The dsPIC33F Interrupt Controller module reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33F CPU. Following are the module features: • • • • • • • Up to eight processor exceptions and software traps Seven user-selectable priority levels Interrupt Vector Table (IVT) with up to 126 vectors Unique vector for each interrupt or exception source Fixed priority within a specified user priority level Alternate Interrupt Vector Table (AIVT) for debugging support Fixed interrupt entry and return latencies