Arm Architecture

ARM Processor Architecture

Some Slides are Adopted from NCTU IP Core Design Some Slides are Adopted from NTU Digital SIP Design Project
SOC Consortium Course Material

Outline
ARM Core Family ARM Processor Core Introduction to Several ARM processors Memory Hierarchy Software Development Summary

SOC Consortium Course Material

2

ARM Core Family

SOC Consortium Course Material

3

ARM Core Family
Application Cores ARM Cortex-A8 ARM Cortex-A9 MPCore ARM Cortex-A9 Single Core ARM11 MPCore ARM1136J(F)-S ARM1176JZ(F)-S ARM720T ARM920T ARM922T ARM926EJ-S Embedded Cores ARM Cortex-M10 ARM Cortex-M1 ARM Cortex-M3 ARM Cortex-R4(F) ARM1156T2(F)-S ARM7EJ-S ARM7TDMI ARM7TDMI-S ARM946E-S ARM966E-S ARM968E-S ARM996HS
SOC Consortium Course Material 4

Secure Cores SecurCore SC100 SecurCore SC110 SecurCore SC200 SecurCore SC210

Product Code Demystified

T: Thumb D: On-chip debug support M: Enhanced multiplier I: Embedded ICE hardware T2: Thumb-2 S: Synthesizable code E: Enhanced DSP instruction set J: JAVA support, Jazelle Z: Should be TrustZone? F: Floating point unit H: Handshake, clockless design for synchronous or asynchronous design
SOC Consortium Course Material 5

ARM Processor Cores (1/4)

ARM processor core + cache + MMU → ARM CPU cores ARM6 → ARM7
– – – – 3-stage pipeline Keep its instructions and data in the same memory system Thumb 16-bit compressed instruction set On-chip Debug support, enabling the processor to halt in response to a debug request – Enhanced Multiplier, 64-bit result – Embedded ICE hardware, give on-chip breakpoint and watchpoint support

SOC Consortium Course Material

6

ARM Processor Cores (2/4)

ARM8 → ARM9 → ARM10 ARM9
– 5-stage pipeline (130 MHz or 200MHz) – Using separate instruction and data memory ports

ARM 10 (1998. Oct.)
– High performance, 300 MHz – Multimedia digital consumer applications – Optional vector floating-point unit
SOC Consortium Course Material 7

ARM Processor Cores