Design & Implementation of a Sequence Detector on an Fpga

Design & Implementation of a Sequence Detector on an FPGA

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EE3076 – Advanced Digital Systems

28th January 2013
Revision 1.0

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Contents

Contents 1 Tables and Figures 3 Revision History 5 1 Introduction 6 1.1 Assignment Objectives 6 1.2 Assignment Description 6 1.3 FPGA Board 7 1.4 Pre – anticipated issue: Switch Bounce 8 2 Design 9 2.1 User Design Specification 9 2.2 High-Level Architecture 9 2.3 Formal Design Specification 10 2.3.1 Clock Divider 10 2.3.2 Keypad Driver 11 2.3.3 Sequence Detector Design 12 2.3.4 LED Driver 14 3 Implementation 15 3.1 Clock Divider 15 3.1.1 Port and Entity Declarations 15 3.1.2 Counter Implemented Clock Divider 16 3.2 Keypad Driver 16 3.2.1 Port and Entity Declaration 16 3.2.2 Keypad Button Translation 17 3.2.3 ‘Key Held Down’ Filter 17 3.2.4 Switch Bounce & Output P Filter 18 3.3 Sequence Detector 19 3.3.1 Port and Entity Declaration 19 3.3.2 Clock Enable Logic 19 3.3.3 Reset Logic and Symbol Counter Driving Logic 19 3.3.4 Next State Logic 20 3.3.5 Output Logic 21 3.4 Led Driver 21 3.4.1 Port and Entity Declaration 21 3.4.2 Led Driving Logic, Pattern Generation and Reset 22 4 Testing & Verification 23 4.1 Clock Divider 23 4.2 Keypad Driver 23 4.3 Sequence Detector 25 4.3.1 Initial Reset 25 4.3.2 State Transitions for Correct Sequence 25 4.3.3 Reset After Correct Sequence Detected 26 4.3.4 State Transition for Incorrect Sequence 27 4.3.5 Output after 25 Symbols Entered 27 4.4 Led Driver 28 4.5 Top-Level Testing 29 5 Conclusion 30

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Tables and Figures

Figure 1:FPGA