DSD HELP

Digital System Design

Introduction to Xilinx
• Xilinx ISE Design Suite.
• File  new project insert project name and select directory.
• Product Category: to be general purpose.
• Family: as Spartan3
• Device: XC3S400
• Package: PQ208NextFinish.

Intro Xilinx Contd..
• In a window at top left corner right click on the created project.
•  New source verilog module  insert name Next
• Mention port name and select port type and its width.
• Next  Finish.
• Your file has been created….

How to simulate in Xilinx
• In a design window at top left select simulation. • In the window select the test fixture that has been created to test.
• In the window below expand “ISim Simulator”
• Double click “Behavioral Check Syntax”.
•  double Click “Simulate Behavioral Model”.
• The resultant WAV is generated.

Lab Task
1. Design a processor using Verilog.
2. Instruction size is [10:0] i.e. 11 bits.
3. Implement:
i.

ii. iii. ALU as a function which takes [2:0]alu_op, [7:0]in1, [7:0]in2 as input and returns a single output of 16 bits i.e. [15:0].
MUX as a function which takes [7:0]in1,[7:0]in2 and sel as input and returns a single output of 8 bits i.e. [7:0]. Use conditional operator.
Control Unit as a task which takes as input [2:0]opcode, and generates 3 output i.e. [2:0]alu_op, reg_write, [3:0]reg_sel.

4. Use these function and task in main module to get the desired working.
5. Create a register file and assign an initial value to each register on negedge rst_n.

Operations
Opcode

Alu_op

operation

reg_write

Reg_sel

000

000

+

1

0000

001

001

-

1

0001

010

010

*

1

0010

011

011

|

1

0011

100

100

~(|)

1

0100

101

101

&

1

0101

110

110

^

1

0110

111

111

~^

1

0111

Main Module
• Input [10:0]instruction,clk,rst_n
• output [15:0]result
• reg
– [7:0]register[0:15], reg_write_main,