Extended Golay Code Analysis
The generated codeword shown in this example has a weight of 12 that is a multiple of four and greater than eight. Thus, the generated codeword is valid.
III. PEROSED BINARYAND EXTENDED GOLAY CODE ARCHITECTURE
In (23, 12, 7) Golay code, the message is constructed of 12 bits, then additional 11 bits are appended to it. After appending check bits, which are obtained from CRC generation process to the 12 bits message, total bits will become 23 and it is named codeword. The 23 bits obtained at the receiver side is able to be converted into a 12 bits message even if there is distortion in the message.The proposed architecture for the binary and extended Golay code is constructed of three sections: 1) data unit or data path, 2) control unit, and …show more content…
Reviriego, S. Liu, L. Xiao, and J. A. Maestro, "An efficient single and double-adjacent error correcting parallel decoder for the (24, 12) extended Golay code," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp. 1603-1606, 2016.
[2] F. J. MacWilliams and N. J. A. Sloane, The theory of error-correcting codes. Elsevier, 1977.
[3] R. W. Hamming, "Error detecting and error correcting codes," Bell Labs Technical Journal, vol. 29, no. 2, pp. 147-160, 1950.
[4] C. E. Shannon, "A mathematical theory of communication," Bell System Technical Journal, vol. 27, no. 1, pp. 379-423, July 1948.
[5] M.J.E.Golay, "Notes on digital coding," Proc.IRE, vol. 37, p. 657, jun. 1949.
[6] S. Sarangi and S. Banerjee, "Efficient hardware implementation of encoder and decoder for Golay code," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1965-1968, …show more content…
Rezai and P. Keshavarzi, "High-performance scalable architecture for modular multiplication using a new digit-serial computation," Microelectronics Journal, vol. 55, pp. 169-178, 2016.
[15] A. Rezai and P. Keshavarzi, "High-throughput modular multiplication and exponentiation algorithms using multibit-scan–multibit-shift technique," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1710-1719, 2015.
[16] S. Lin and D. Costello, "Error control coding, 2nd edEnglewood Cliffs," ed: Prentice-Hall, 2010.
[17] S. Gowri and K. Ribana, "High-speed encoder and decoder of the binary Golay code," Journal of Chemical and Pharmaceutical Sciences ISSN, vol. 974, p. 2115, 2017.
[18] F. McWilliams and N. Sloane, "The theory of error correcting codes, North-Holland," ed: Amsterdam, 1977.
[19] W. W. Peterson and E. J. Weldon, Error-correcting codes. MIT press, 1972.
[20] T. K. Moon, "Error correction coding," Mathematical Methods and Algorithms. Jhon Wiley and Son, 2005.
[21] U. Rangare and R. Thakur, "A review on design and simulation of extended Golay decoder," International Journal of Engineering Science, vol. 2058, 2016.
[22] G. Campobello, G. Patane, and M. Russo, "Parallel CRC realization," IEEE Transactions on Computers, vol. 52, no. 10, pp. 1312-1319,
III. PEROSED BINARYAND EXTENDED GOLAY CODE ARCHITECTURE
In (23, 12, 7) Golay code, the message is constructed of 12 bits, then additional 11 bits are appended to it. After appending check bits, which are obtained from CRC generation process to the 12 bits message, total bits will become 23 and it is named codeword. The 23 bits obtained at the receiver side is able to be converted into a 12 bits message even if there is distortion in the message.The proposed architecture for the binary and extended Golay code is constructed of three sections: 1) data unit or data path, 2) control unit, and …show more content…
Reviriego, S. Liu, L. Xiao, and J. A. Maestro, "An efficient single and double-adjacent error correcting parallel decoder for the (24, 12) extended Golay code," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp. 1603-1606, 2016.
[2] F. J. MacWilliams and N. J. A. Sloane, The theory of error-correcting codes. Elsevier, 1977.
[3] R. W. Hamming, "Error detecting and error correcting codes," Bell Labs Technical Journal, vol. 29, no. 2, pp. 147-160, 1950.
[4] C. E. Shannon, "A mathematical theory of communication," Bell System Technical Journal, vol. 27, no. 1, pp. 379-423, July 1948.
[5] M.J.E.Golay, "Notes on digital coding," Proc.IRE, vol. 37, p. 657, jun. 1949.
[6] S. Sarangi and S. Banerjee, "Efficient hardware implementation of encoder and decoder for Golay code," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1965-1968, …show more content…
Rezai and P. Keshavarzi, "High-performance scalable architecture for modular multiplication using a new digit-serial computation," Microelectronics Journal, vol. 55, pp. 169-178, 2016.
[15] A. Rezai and P. Keshavarzi, "High-throughput modular multiplication and exponentiation algorithms using multibit-scan–multibit-shift technique," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1710-1719, 2015.
[16] S. Lin and D. Costello, "Error control coding, 2nd edEnglewood Cliffs," ed: Prentice-Hall, 2010.
[17] S. Gowri and K. Ribana, "High-speed encoder and decoder of the binary Golay code," Journal of Chemical and Pharmaceutical Sciences ISSN, vol. 974, p. 2115, 2017.
[18] F. McWilliams and N. Sloane, "The theory of error correcting codes, North-Holland," ed: Amsterdam, 1977.
[19] W. W. Peterson and E. J. Weldon, Error-correcting codes. MIT press, 1972.
[20] T. K. Moon, "Error correction coding," Mathematical Methods and Algorithms. Jhon Wiley and Son, 2005.
[21] U. Rangare and R. Thakur, "A review on design and simulation of extended Golay decoder," International Journal of Engineering Science, vol. 2058, 2016.
[22] G. Campobello, G. Patane, and M. Russo, "Parallel CRC realization," IEEE Transactions on Computers, vol. 52, no. 10, pp. 1312-1319,