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Instruction Cache Memory Issues in Real-Time Systems
Filip Sebek
Computer Architecture Lab Department of Computer Science and Engineering Technology licentiate thesis 2002-10 ISBN 97-88834-38-7
(13th September 2002)
Instruction Cache Memory Issues in Real-Time Systems
Filip Sebek
Department of Computer Science and Engineering Mälardalen University Västerås, Sweden
Abstract
Cache memories can contribute to significant performance advantages due to the gap between CPU and memory speed. They have traditionally been thought of as contributors to unpredictability because the user can not be sure of exactly how much time will elapse while a memory-operation is performed. In a real-time system, the cache memory may contribute to a missed deadline by actually making the system slower, but this is rare. To avoid this problem, the developers of real-time systems have run the program in the old-fashioned way; with disabled cache — just to be safe. Turning the cache off, however, will also make other features like instruction pipelining less beneficial so the new processors will not give the performance speedup as they were meant to give. The first methods to determine the boundaries of the execution time in computer systems with cache memories were presented in the late eighties — twenty years after the first cache memories were designed. Today, fifteen years later, further methods have been developed to determine the execution time with cache memories . . . that were state-of-the-art fifteen years ago. This thesis presents a method of generating worst-case execution time scenarios and measure the execution time during those. Several important properties can be measured. These include cache-related pre-emption delay, missratio levels of software, and instruction cache miss-ratio threshold levels for increased system performance. Besides the dynamic measurement method, a statical procedure to determine the maximum instruction cache miss-ratio level is presented.
Filip Sebek
Computer Architecture Lab Department of Computer Science and Engineering Technology licentiate thesis 2002-10 ISBN 97-88834-38-7
(13th September 2002)
Instruction Cache Memory Issues in Real-Time Systems
Filip Sebek
Department of Computer Science and Engineering Mälardalen University Västerås, Sweden
Abstract
Cache memories can contribute to significant performance advantages due to the gap between CPU and memory speed. They have traditionally been thought of as contributors to unpredictability because the user can not be sure of exactly how much time will elapse while a memory-operation is performed. In a real-time system, the cache memory may contribute to a missed deadline by actually making the system slower, but this is rare. To avoid this problem, the developers of real-time systems have run the program in the old-fashioned way; with disabled cache — just to be safe. Turning the cache off, however, will also make other features like instruction pipelining less beneficial so the new processors will not give the performance speedup as they were meant to give. The first methods to determine the boundaries of the execution time in computer systems with cache memories were presented in the late eighties — twenty years after the first cache memories were designed. Today, fifteen years later, further methods have been developed to determine the execution time with cache memories . . . that were state-of-the-art fifteen years ago. This thesis presents a method of generating worst-case execution time scenarios and measure the execution time during those. Several important properties can be measured. These include cache-related pre-emption delay, missratio levels of software, and instruction cache miss-ratio threshold levels for increased system performance. Besides the dynamic measurement method, a statical procedure to determine the maximum instruction cache miss-ratio level is presented.