X Masking Techniques and Test Data Compaction of Logic Bist
B.E. PROJECT ON X-MASKING TECHNIQUES AND TEST DATA COMPACTION FOR LOGIC BUILT-IN SELF TEST
A DISSERTATION SUBMITTED TOWARDS THE PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE AWARD OF A DEGREE IN BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION Submitted By
HIMANSHU DOVAL VARUN KAPOOR (2K7/EC/643) (2K7/EC/713)
UNDER THE GUIDANCE OF
DR. ASOK BHATTACHARYYA
DEPARTMENT OF ELECTRONICS AND COMMUNICATION DELHI COLLEGE OF ENGINEERING 2011
ABSTRACT
Testing is done for checking the integrated circuits for manufacturing faults introduced during semiconductor processing. Testing typically consists of applying a set of test stimuli to the inputs of the circuit under test (CUT) while analyzing the output responses. An Automated test Equipment (ATE) is used to generate the test stimuli and analyze the output.
Logic built-in self-test (LBIST) is a design for testability (DFT) technique in which a portion of a circuit on a chip, board, or system is used to test the digital logic circuit itself. A typical logic BIST system contains a test pattern generator (TPG) which automatically generates test patterns for application to the inputs of the circuit under test; an output response analyzer (ORA) which automatically compacts the output responses of the CUT into a signature. This signature is compared with a golden signature to decide whether the chip contains manufacturing faults. The most significant advantage of LBIST is that it does not require the expensive ATE and it makes on-field testing possible.
To make Logic BIST solution practically applicable there are a few problems which one has to deal with. These are associated with the hardware as well as with the software. Hardware (Multiple Input Shift Register) needs to be protected from the flow of don’t cares and software issues deal with the Test data Compaction which is necessary so as to reduce the on chip tester memory. ii
CERTIFICATION
This is to certify that the project entitled “LOGIC
A DISSERTATION SUBMITTED TOWARDS THE PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE AWARD OF A DEGREE IN BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION Submitted By
HIMANSHU DOVAL VARUN KAPOOR (2K7/EC/643) (2K7/EC/713)
UNDER THE GUIDANCE OF
DR. ASOK BHATTACHARYYA
DEPARTMENT OF ELECTRONICS AND COMMUNICATION DELHI COLLEGE OF ENGINEERING 2011
ABSTRACT
Testing is done for checking the integrated circuits for manufacturing faults introduced during semiconductor processing. Testing typically consists of applying a set of test stimuli to the inputs of the circuit under test (CUT) while analyzing the output responses. An Automated test Equipment (ATE) is used to generate the test stimuli and analyze the output.
Logic built-in self-test (LBIST) is a design for testability (DFT) technique in which a portion of a circuit on a chip, board, or system is used to test the digital logic circuit itself. A typical logic BIST system contains a test pattern generator (TPG) which automatically generates test patterns for application to the inputs of the circuit under test; an output response analyzer (ORA) which automatically compacts the output responses of the CUT into a signature. This signature is compared with a golden signature to decide whether the chip contains manufacturing faults. The most significant advantage of LBIST is that it does not require the expensive ATE and it makes on-field testing possible.
To make Logic BIST solution practically applicable there are a few problems which one has to deal with. These are associated with the hardware as well as with the software. Hardware (Multiple Input Shift Register) needs to be protected from the flow of don’t cares and software issues deal with the Test data Compaction which is necessary so as to reduce the on chip tester memory. ii
CERTIFICATION
This is to certify that the project entitled “LOGIC