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LABORATORY
MANUAL
ECE 420
Digital VLSI Design

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Content
Experiment
No.
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Name of Experiment

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Write a program in Verilog to implement all logic gates.
Write a program in verilog to implement half adder/full adder/subtractor
Write a program in verilog to implement multiplexer/demultiplexer Write a program in verilog to implement decoder/encoder Write a program in verilog to implement 4 bit parallel adder using Gate level modelling
Introduction to experiments after MTP

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Introduction to Xilinx experiments before MTP

Tool Used software and Xilinx 12.4

Xilinx 12.4
Xilinx 12.4
Xilinx 12.4
Xilinx 12.4
Xilinx 12.4
Xilinx 12.4

Write a program in verilog to implement 4 Xilinx 12.4 bit ALU
Write a program in verilog to implement Xilinx 12.4 code converters
Write a program in verilog to implement flip Xilinx 12.4 flops Write a program in verilog to implement Xilinx 12.4 counters Write a program in verilog to implement Xilinx 12.4 sequence detector(0110/10101)

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EXPERIMENT- 1
AIM: Introduction to Xilinx (ISE) Software and experiments before
MTP
ISE controls all aspects of the design flow. Through the Project Navigator interface, you can access all of the design entry and design implementation tools. You can also access the files and documents associated with your project. Project Navigator maintains a flat directory structure.
Project Navigator Interface:
The Project Navigator Interface is divided into four main sub windows. On the top left is the Sources window which hierarchically displays the elements included in the project.
Beneath the Sources window is the Processes window, which displays available processes for the currently selected source. The third window at the bottom of the Project
Navigator is the Transcript window which displays status messages, errors, and warnings and also contains interactive tabs for Tcl scripting and the Find in Files