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junctionless nanowire transistor

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junctionless nanowire transistor
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PUBLISHED ONLINE: 21 FEBRUARY 2010 | DOI: 10.1038/NNANO.2010.15

Nanowire transistors without junctions
Jean-Pierre Colinge*, Chi-Woo Lee, Aryan Afzalian†, Nima Dehdashti Akhavan, Ran Yan,
Isabelle Ferain, Pedram Razavi, Brendan O’Neill, Alan Blake, Mary White, Anne-Marie Kelleher,
Brendan McCarthy and Richard Murphy
All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult fabrication challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

A

ll existing transistors are based on the formation of junctions.
Junctions are capable of both blocking current and allowing it to flow, depending on an applied bias. They are typically formed by placing two semiconductor regions with opposite polarities into contact with one another. The most common junction is the p–n junction, which consists of a contact between a p-type piece of silicon, rich in holes, and an n-type piece of silicon, rich in electrons. Every textbook on semiconductor device physics contains a chapter on the p–n junction, usually between the introductory chapters on semiconductor material fundamentals and the chapters dedicated to the different types of transistors.
Other types of junctions include the metal–silicon ‘Schottky’ junction and the



References: 1. Lilienfeld, J. E. Method and apparatus for controlling electric current. US patent 1,745,175 (1925). 2. Lilienfeld, J. E. Device for controlling electric current. US patent 1,900,018 (1928). analytical model. Ultimate Integration on Silicon Conference (ULIS) 18–20 Poster 249 (2009). 6. Lee, C. W. et al. Junctionless multigate field-effect transistor. Appl. Phys. Lett. 94, 053511 (2009). IEEE Electron. Dev. Lett. 24, 263–265 (2003). 12. Colinge, J. P. FinFETs and Other Multi-Gate Transistors (Springer, 2007). enhancement-mode. IEEE 2008 Silicon Nanoelectronics Workshop P1–6 (2008). FinFETs. International Conference on Solid-State and Integrated Circuit Technology 72–74 (2006). 245–248 (2008).

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