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To Improve Register File Integrity Against Soft Errors Using Self-Immunity Technique

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To Improve Register File Integrity Against Soft Errors Using Self-Immunity Technique
To Improve Register File Integrity against Soft Errors Using Self-Immunity Technique

G.Suvarna susi
P.G Student,
Sri Vishnu Engineering College For Women,
Bhimavaram,
Andhra Pradesh.
E-mail:suvarna.susi@gmail.com

D.Murali Krishna
Sr Assistant.Professor,
ECE Department,
Sri Vishnu Engineering College For Women, Bhimavaram, Andhra Pradesh.
E-mail: mkrishna557@gmail.com

Abstract—Continuous shrinking in feature size, increasing power density etc. increase the vulnerability of microprocessors against soft errors even in terrestrial applications. The register file is one of the essential architectural components where soft errors can be very mischievous because errors may rapidly spread from there throughout the whole system. Thus, register files are recognized as one of the major concerns when it comes to reliability. This paper introduces Self-Immunity, a technique that improves the integrity of the register file with respect to soft errors. Based on the observation that a certain number of register bits are not always used to represent a value stored in a register. This paper deals with the difficulty to exploit this obvious observation to enhance the register file integrity against soft errors. We show that our technique can reduce the vulnerability of the register file considerably while exhibiting smaller overhead in terms of area and power consumption compared to state-of-the-art in register file protection. I.INTRODUCTION
Over the last decade, and in spite of the increasingly complex architectures, and the rapid growth of new technologies, the technology scaling has raised soft errors tobecome one of the major sources for processor crashing in many systems in the nanoscale era. Soft errors caused by charged particles are dangerous primarily in highatmospheric, where heavy alpha particles are available.However, trends in today’s nanometer technologies such as aggressive shrinking have made low-energy particles,



References: [4] Jongeun Lee and A. Shrivastava, “A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files,” in Computer-Aided Design of Integrated Circuits and Systems, pp. 1018-1027, 2010. [6] G. Memik, M.T. Kandemir and O. Ozturk, “Increasing register file immunity to transient errors,” in Design, Automation and Test in Europe, pp. 586-591, 2005. [8] Jason A. Blome, Shantanu Gupta, Shuguang Feng, and Scott Mahlke, “Cost-efficient soft error protection for embedded microprocessors,” in CASES ’06, pp. 421–431, 2006. [9] P. Montesinos, W. Liu, and J. Torrellas, “Using register lifetime predictions to protect register files against soft errors,” in Dependable Systems and Networks, pp. 286–296, 2007. [10] M. Rebaudengo, M. S. Reorda, and M.Violante, “An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor,” in DATE’03, pp. 602-607, 2003. [11] T. Slegel et al, “IBM’s S/390 G5 microprocessor design,” in IEEE Micro, 19, pp. 12-23, 1999. [13] K. Walther, C. Galke and H.T. VIERHAUS, “On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check,” in Journal of Electronic Testing: Theory and Applications 19, pp.501-510, 2003. [14] M. Spica and T.M. Mak, “Do we need anything more than single bit error correction (ECC)?,“ in Memory Technology, Design and Testing, Records of the International Workshop on 9-10, pp. 111– 116, 2004.

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