Vhdl
Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition By Samir Palnitkar Publisher: Prentice Hall PTR Pub Date: February 21, 2003 ISBN: 0-13-044911-3 Pages: 496
Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard. • • • • • • • Describes state-of-the-art verification methodologies Provides full coverage of gate, dataflow (RTL), behavioral and switch modeling Introduces you to the Programming Language Interface (PLI) Describes logic synthesis methodologies Explains timing and delay simulation Discusses user-defined primitives Offers many practical modeling tips
Includes over 300 illustrations, examples, and exercises, and a Verilog resource list.Learning objectives and summaries are provided for each chapter.
Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition By Samir Palnitkar Publisher: Prentice Hall PTR Pub Date: February 21, 2003 ISBN: 0-13-044911-3 Pages: 496
2
Copyright
2003 Sun Microsystems, Inc. 2550 Garcia Avenue, Mountain View, California 940431100 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX system and from the Berkeley 4.3 BSD system, licensed from the University of California. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun's Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in
Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard. • • • • • • • Describes state-of-the-art verification methodologies Provides full coverage of gate, dataflow (RTL), behavioral and switch modeling Introduces you to the Programming Language Interface (PLI) Describes logic synthesis methodologies Explains timing and delay simulation Discusses user-defined primitives Offers many practical modeling tips
Includes over 300 illustrations, examples, and exercises, and a Verilog resource list.Learning objectives and summaries are provided for each chapter.
Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition By Samir Palnitkar Publisher: Prentice Hall PTR Pub Date: February 21, 2003 ISBN: 0-13-044911-3 Pages: 496
2
Copyright
2003 Sun Microsystems, Inc. 2550 Garcia Avenue, Mountain View, California 940431100 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX system and from the Berkeley 4.3 BSD system, licensed from the University of California. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun's Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in