Vhdl Project Report
Design of Quantizer with Signed Quantization Level (3 downto -4)
Mini Project Report
VHDL and Digital Design
Table of Contents | | Page No | 1 | Introduction | 4 | | 1.1 | Fixed Point Package | 5 | | 1.2 | IEEE floating-point representations of real numbers | 5 | | 1.3 | Results & Discussion | 8 | 2. | Conclusion | 20 | | Bibliography | 20 | Appendix A: | | | VHDL Test Bench code Quantizer with Signed Quantization Level (3 downto -4) | 21 |
List of Figures: Figure 1 : | Block Diagram of Complete Simulation Model | Figure 2: | Binary to Octal Encoder and corresponding decoder system | Figure 3: | Xilinx ISE simulator’s testbech waveform output for a real value input 2.93893 |
Chapter 1
Introduction
In this work we have designed a digital 8-bit quantizer to reduce the number of bits involved in representing a real valued sample to a fixed point representation with reduced number of bits. The work also involved designed of a Binary to Octal encoder and corresponding decoder. The implementation of encoder-decoder involved conversion of the Fixed point number to Standard Logic vector. After the encoding and decoding process the Slandered Logic vector is converted back to Fixed point number then back to Real Number representation. Quantization error is calculated form the difference between input and output real numbers. We have utilized Xilinx ISE simulator and IEEE proposed Fixed Point package during execution of the projects. Figure 1 shows the block diagram representation of the proposed system.
INPUT
(Type: Real)
Sample Values
Real To Fixed Point Conversion
Signed Quantization Level (3 downto -4)
Resolution (0.0625)
Fixed Point to
IEEE Standard Bit Vector Conversion
Hex Encoding
Binary to Octal Encoding / Encryption
Hex Encoding
Octal to Binary Decoding / Decryption
Hex Encoding
IEEE Standard Bit Vector to Fixed Point Conversion
Fixed Point To
Conversion
Real Type Conversion
Mini Project Report
VHDL and Digital Design
Table of Contents | | Page No | 1 | Introduction | 4 | | 1.1 | Fixed Point Package | 5 | | 1.2 | IEEE floating-point representations of real numbers | 5 | | 1.3 | Results & Discussion | 8 | 2. | Conclusion | 20 | | Bibliography | 20 | Appendix A: | | | VHDL Test Bench code Quantizer with Signed Quantization Level (3 downto -4) | 21 |
List of Figures: Figure 1 : | Block Diagram of Complete Simulation Model | Figure 2: | Binary to Octal Encoder and corresponding decoder system | Figure 3: | Xilinx ISE simulator’s testbech waveform output for a real value input 2.93893 |
Chapter 1
Introduction
In this work we have designed a digital 8-bit quantizer to reduce the number of bits involved in representing a real valued sample to a fixed point representation with reduced number of bits. The work also involved designed of a Binary to Octal encoder and corresponding decoder. The implementation of encoder-decoder involved conversion of the Fixed point number to Standard Logic vector. After the encoding and decoding process the Slandered Logic vector is converted back to Fixed point number then back to Real Number representation. Quantization error is calculated form the difference between input and output real numbers. We have utilized Xilinx ISE simulator and IEEE proposed Fixed Point package during execution of the projects. Figure 1 shows the block diagram representation of the proposed system.
INPUT
(Type: Real)
Sample Values
Real To Fixed Point Conversion
Signed Quantization Level (3 downto -4)
Resolution (0.0625)
Fixed Point to
IEEE Standard Bit Vector Conversion
Hex Encoding
Binary to Octal Encoding / Encryption
Hex Encoding
Octal to Binary Decoding / Decryption
Hex Encoding
IEEE Standard Bit Vector to Fixed Point Conversion
Fixed Point To
Conversion
Real Type Conversion