Cordic Sine and Cosine

FPGA Implementation of CORDIC Processor
Gaurav D. Bhand1, Prabha Kasliwal2
1 PG Student Department of Electronics, MIT Academy of Engineering, Pune University
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Abstract— Many hardware efficient algorithms exists but these are not well known due to dominance of software systems over the past many years. Among these algorithms there is a simple shift-add algorithm known as CORDIC. CORDIC is being widely used in many domains like Image Processing, Communication, Robotics, Signal Processing applications due to its simple hardware efficient algorithm which is based on shift and add hardware. As CORDIC occupies less gate count in FPGA, it has been drawing attentions among many researchers and efforts have been made to improve its throughput and power keeping the constraints in mind. This paper summarizes the CORDIC architectures, presents a simulation of basic CORDIC cell and Implements Unfolded CORDIC Architecture on Spartan XC3S50 FPGA family. Keywords— CORDIC, Sine, Cosine, FPGA, CORDIC throughput

III. In Section IV we discuss the implementation of CORDIC algorithm in an FPGA and the simulation of basic CORDIC cell using Xilinx tool and XC3S50 Spartan3 family of FPGA is presented. The conclusion along with future research directions are discussed in Section V. II. CORDIC PRINCIPLE The CORDIC algorithm is based on the fact that any number may be represented by an appropriate alternating series. For example an appropriate value for e may be represented as e = 3- 0.3 + 0.02 - 0.002 + 0.0003 = 2.7183. The CORDIC technique uses a similar method of computation. There are two modes of operation for a CORDIC processor. a) Rotation Mode

I. INTRODUCTION Coordinate Rotation Digital Computer is abbreviated as CORDIC. Its implementation was first described in 1959 by Jack E. Volder [1], for the computation of trigonometric functions, multiplication and division. Further work has been carried out by J. S.

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